* m68k/n68kcnv.pas, tm68ktypeconvnode.second_int_to_bool:
Take an inspiration from the x86 code generator and correctly handle assignment of values with a size < 8 to 64-bit Booleans
git-svn-id: trunk@26847 -
m68k/cgcpu.pas, tcg68k:
+ override g_adjust_self_value as we don't do register allocation for the wrapper we need to adjust the Self value using the scratch registers (could be improved however) and we also can not use the offset that the original procedure in tcg uses
* fix g_intf_wrapper by using the correct operations and loading the correct (virtual) method offset
git-svn-id: trunk@25728 -
m68k/cgcpu.pas, tcg68k:
- remove g_save_registers and g_restore_registers which DID NOT CALL inherited!
- also remove commented methods g_save_all_registers & g_restore_all_registers
git-svn-id: trunk@25715 -
- removed the ancient DEBUG_CHARLIE silliness... :)
- moved some repeated code patterns into separate functions
- rewrote most of of tcg68k.a_op_const_reg and tcg68k.a_op_reg_reg
- smarter code generation in tcg68k.a_cmp_const_reg_label
- added support for MULU/MULS on Coldfire in a case which is often used by the CG to index arrays to be used instead of the RTL helpers, this results in a *HUGE* speedup in tw5086 for example
git-svn-id: trunk@25702 -
cgobj.pas, tcg:
* g_save_registers: add the amount of used address registers to size as well
* g_save_registers: save all used address registers
* g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
* rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
* add a saved_address_registers variable with one entry of RS_INVALID
At least a "make fullcycle" did complete.
git-svn-id: trunk@25664 -
m68k/cgcpu.pas, tcg68k.g_proc_exit:
* use A0 (which is a volatile register) instead of A3 (which is not) to restore the stack pointer
git-svn-id: trunk@25663 -
this fixes varargs a bit, particularly fixes an unhandled TList bounds exception while compiling packages/fcl-base/src/eventlog.pp
git-svn-id: trunk@25636 -
paramgr.pas, tparamanager:
+ add virtual get_volatile_registers_address method which by default returns an empty set
cgobj.pas, tcg:
* allocallcpuregisters: also allocate address registers if needed
* deallocallcpuregisters: also deallocate address registers if needed
ncgcal.pas, tcgcallnode.pass_generate_code:
* (de)allocate address registers
* keep result from being deallocated if it should be an address register (currently by no architecture...)
m68k/cpupara.pas, tm68kparamanager:
+ get_volatile_registers_address: return a0 and a1 as volatile registers
m68k/n68kmat.pas, tm68kmoddivnode.call_rtl_divmod_reg_reg:
* (de)allocate address registers
git-svn-id: trunk@25633 -
m68k/n68kadd.pas, tn68kadd.second_cmpordinal:
* use the size of the largest operand to select a fiting operand
* ToDo: check whether a sign/zero extend of the value is necessary
git-svn-id: trunk@25628 -
m68k/n68kcnv.pas, tn68kcnv.second_int_to_bool:
* we need to check both the upper and the lower register for a 64-bit value to decide whether it's True or False
git-svn-id: trunk@25625 -
m68k/cgcpu.pas, tcg68k:
* a_load_ref_cgpara: use pashsize instead of paraloc^.size as the latter could be OS_NO and thus a "move" instead of a "move.x" will be generated resulting in a word move when a long or byte move might have been necessary
* a_load_reg_ref: use the smallest size when moving the value to a reference
* a_load_ref_ref: when the size is different always use a temporary register for a ref to ref move
* a_load_ref_ref: when doing a fixed move for Coldfire use the correct ref (that's another embarrasing error...) and size (fixes usage of String[Index] for a const array parameter)
* a_load_ref_reg: use the smallest size when moving the value from a reference
* g_concatcopy: don't use source.alignment as that doesn't contain the correct value and also load the value into the temp register using the correct size (fixes passing of small values as parameters, like chars)
git-svn-id: trunk@25624 -
m68k/cgcpu.pas, tcg68k.g_flags2reg:
* don't sign extend the flag value which was stored to the register, but instead do a "AND 1" on it to reduce it to 1 bit; afterall Booleans in Pascal are either 0 or 1 and not 0 or $FF
+ added test
git-svn-id: trunk@25598 -
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.
fpcdefs.inc:
+ define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
* check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
- the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
- tcputype: remove "cpu_coldfire"
+ tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
+ add "cpu_coldfire" constant which contains all Coldfire specific cpu types
* adjust "cputypestr" and "gascputypestr"
+ add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
* adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
* don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
* adjusted check for Coldfire
git-svn-id: trunk@25457 -
contains the tcgsize of the entire parameter rather than only of
what is left (-> calculate it from the remaining parameter length)
git-svn-id: trunk@24776 -
m68k/cgcpu.pas, tcg68k:
+ overload "a_loadfpu_ref_cgpara" and use the 64-bit code generator to pass Doubles if they are located in references
Fixes around nearly 100 tests.
git-svn-id: trunk@23597 -
* initialize paraloc^.size to OS_INT instead of leaving it at 0
This fixes tests/test/cg/ttryexc1.pp. The problem was that the raise node generated code which resulted in a word(!) move of the raised object's address to the stack location for fpc_raiseexception. This then resulted in an error when freeing the exception object.
git-svn-id: trunk@23465 -
m68k/aasmcpu.pas, taicpu.spilling_get_operation_type:
* add all Sxx instructions as "operand_write" instructions
m68k/n68kadd.pas, t68kaddnode.getresflags:
* use the correct operation in case of swapped nodes
m68k/cgcpu.pas, tcg68k.g_flags2reg:
- don't move a 0 to the register, because this will CLR it and thus the flags won't be valid anymore...
- NEG would have been the wrong operation (NOT would have been correct), but it isn't needed anyway...
* simplify the method by handling the address register case only when necessary
git-svn-id: trunk@23383 -
use the correct flag for the copy loop: we jump back to the copy code as long as the value is positive aka BPL instead of BMI
This fixes around 30 tests (it fixes a quite bit more, but now some other tests seem to be broken...)
git-svn-id: trunk@23373 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
+ a_op64_reg_reg: add support for "NEG" and "NOT" of 64-bit values
+ a_op64_const_reg: make sure that we know whether a NEG or NOT with a constant is performed
git-svn-id: trunk@22930 -
* in case of copying from the parameter location to the local location we need to use the alignment size for the source as byte/word values are passed as LongInts (this is how the ABI is specified)
git-svn-id: trunk@22924 -
+ add routine "call_rtl_moddiv_reg_reg" which handles the calling of "fpc_div_longint", "fpc_div_dword", "fpc_mod_longint" and "fpc_mod_dword"
* emit_mod_reg_reg & emit_div_reg_reg: use the new method instead of doing the call oneself
=> "Str(SomeInt, SomeStr)" and "Writeln(SomeInt)" now works
git-svn-id: trunk@22893 -
+ add methods "call_rtl_mul_const_reg" and "call_rtl_mul_reg_reg" which can call the RTL helpers "fpc_mul_longint" and "fpc_mul_longword" (based on AVR code)
* use the new call methods for the RTL to correctly pass the parameters (on the stack, not in registers...)
git-svn-id: trunk@22892 -
* don't do a sign_extend, but use the correct move size to copy the const; this fixes the setting of the line ending style inside of "Assign"
=> output of strings does now work correctly!
git-svn-id: trunk@22890 -
TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.
r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.
git-svn-id: trunk@22817 -
for "CMP" it is important to note that the first operand (which can be basically a register, a constant or a reference) is substracted from the second operand (which needs to be a data register) and not the other way round
git-svn-id: trunk@22798 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
fix the double running of second_pass in the way it was intended to work: check for left.expectloc instead of left.location.loc
git-svn-id: trunk@22788 -
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL->
FPC_MOD_DWORD).
Also disable the usage of FPU opcodes for Coldfire.
git-svn-id: trunk@22739 -
M68000 CPUs they are nevertheless more restricted in some cases, so these need to be
handled explicitely (especially if symbols are involved).
git-svn-id: trunk@22738 -
* generate special return code for non-68020 CPU which don't support RTD instruction (based on
out code a few lines further down)
git-svn-id: trunk@22736 -
It seems that GNU as needs the syntax "offset(register.size*scale)" if the base address
register is ommited instead of "offset(,register.size*scale)". Now the System unit
assembles and nearly the complete RTL can be built.
git-svn-id: trunk@22734 -
leave "and" and "or" as "and" and "or" as according to the assembly language reference the
assembler should automatically choose the correct instruction (though Coldfire still should
be tested for ORI/ANDI to CCR
git-svn-id: trunk@22733 -
* use andi/ori for constant values
* use a scratch register if target is an address register (there seems to exist an omnious
anda/ora instruction though, but GNU as doesn't seem to handle it... maybe I haven't set
the CPU type correctly, so I'll need to investigate this so we can hopefully remove the
need for a scratch register for certain CPU types ;) )
git-svn-id: trunk@22732 -
* remove comments regarding needed LOC_JUMP implementation
* don't call flags2reg if the location is LOC_JUMP as there isn't a register to set the flags to
(this allows fpc_mul_qword and fpc_mul_int64 to be assembled)
git-svn-id: trunk@22731 -
implement case "LOC_JUMP" (with a more or less blindly copy from
x86/nx86cnv.pas, tx86typeconvnode.second.int_to_bool; this now allows that the system unit can
be compiled, but not yet assembled
git-svn-id: trunk@22728 -
the asmr_d_*_reading messages need an argument which specifies in which style the assembler code
is read; this is most importantly used on i386; on m68k we currently don't have multiple styles,
so simply disable these messages
git-svn-id: trunk@22725 -
like field reordering (possible problems cracker classes) or using ebp as normal register (broken
stack traces from dump_stack)
+ niln is also valid in a cse domain
* parameters passed by reference shall have a complexity >1
* load nodes from outer scopes shall have a complexity >1
* better cse debugging
+ more node types added to cse
* consider parameters passed by reference in cse
* take care of cse in parameters in simple cases
git-svn-id: trunk@22050 -
order to minimise memory losses due to alignment padding. Not yet enabled
by default at any optimization level, but can be (de)activated separately
via -Oo(no)orderfields
o added separate tdef.structalignment method that returns the alignment
of a type when it appears in a record/object/class (factors out
AIX-specific double alignment in structs)
o changed the handling of the offset of a delegate interface
implemented via a field, by taking the field offset on demand
rather than at declaration time (because the ordering optimization
causes the offsets of fields to be unknown until the entire
declaration has been parsed)
git-svn-id: trunk@21947 -
getintparaloc + adapted all call sites of getintparaloc. This
led to a number of additional, related changes:
o corrected the type information for some getintparaloc parameters
o don't allocate some intparalocs in cases they aren't used
o changed "const tvardata" parameter into "constref tvardata" for
fpc_variant_copy_overwrite to make pass-by-reference semantics
explicit
o moved a number of routines that now have to call find_system_type()
from cgobj to hlcgobj so that cgobj doesn't have to start depending
on the symtable unit
o added versions of the cpureg alloc/dealloc methods to hlcgobj that
call through to their cgobj counter parts, so we can call save/restore
the cpu registers before/after calling system helpers from hlcgobj
(not implemented in hlcgobj itself, because all basic register
allocator functionality is still part of cgobj/cgcpu)
git-svn-id: trunk@21696 -
* set tcgpara.def for the function return location (field introduced for and
already used by the JVM code generator, required for future hlcg
functionality)
git-svn-id: trunk@21691 -
cgutils, and define them so they are no larger than what is required by
the current target platform
* added cgutils to the uses clause of several units that use the
tcpuregisterset type
git-svn-id: trunk@21624 -
RS_INVALID superregister (instead of sometimes RS_NO and sometimes
RS_INVALID)
* check for RS_INVALID in tcg.g_save_registers() and ignore such entries
git-svn-id: trunk@21622 -
future use by high level code generator targets
o this in turn required that all a_load*_loc* methods are called via
hlcg rather than via cg, since a location can be a subsetref/reg and
and those are no longer handled in tcg
o that then required moving several force_location_* routines into
thlcg because they use a_load_loc*, but did not take tdef size
parameters (which are required by the thlcg a_load_loc* routines)
o the only practical consequence is that from now on, you have to
use hlcg.location_force_mem/reg() (fpureg not yet) and
hlcg.gen_load_loc_cgpara() instead of the removed versions from ncgutil,
and hlcg.a_load*loc*() instead of cg.a_load*loc* if a subsetref/reg
might be involved
git-svn-id: trunk@21287 -
o support for the new codepage-aware ansistrings in the jvm branch
o empty ansistrings are now always represented by a nil pointer rather than
by an empty string, because an empty string also has a code page which
can confuse code (although this will make ansistrings harder to use
in Java code)
o more string helpers code shared between the general and jvm rtl
o support for indexbyte/word in the jvm rtl (warning: first parameter
is an open array rather than an untyped parameter there, so
indexchar(pcharvar^,10,0) will be equivalent to
indexchar[pcharvar^],10,0) there, which is different from what is
intended; changing it to an untyped parameter wouldn't help though)
o default() support is not yet complete
o calling fpcres is currently broken due to limitations in
sysutils.executeprocess() regarding handling unix quoting and
the compiler using the same command lines for scripts and directly
calling external programs
o compiling the Java compiler currently requires adding ALLOW_WARNINGS=1
to the make command line
git-svn-id: branches/jvmbackend@20887 -
of the AVR-specific ifdef'ed variant
o since the only special character we use in mangled names on all platforms
is $, added a new field to tasminfo called "dollarsign" that holds the
character $'s should be replaced with (if it doesn't have to be replaced,
leave it at $)
git-svn-id: trunk@20801 -
since the definition-specific adorning of JVM mangled names is Jasmin-
specific, and such code has no place in symdef
* moved code to adorn JVM mangled names for Jasmin definitions to agjasmin
git-svn-id: branches/jvmbackend@18346 -
whether the mangled name is for defining a symbol, or for referencing
it later (e.g. for a call or load of its address). The reason is that
on the JVM both cases are different.
+ jvmdef unit to encode types according to the JVM rules
+ tprocdef.jvmmangledname() to encode a procdef's JVM mangled name
(the common part of defining/referencing it; tprocdef.mangledname
afterwards adorns it as required)
git-svn-id: branches/jvmbackend@18288 -
* $CPU/cgcpu.pas: disable the generation of VMT loading code
* dbgstabs.pas, dbgdwarf.pas: treat virtual methods of helpers as normal methods
* ncgcal.pas: don't register virtual helper methods for WPO
* ncgrtti.pas: write virtual helper methods as normal methods to RTTI
* nobj.pas: correctly handle final and override cases in helpers
* pdecvar.pas: property getters
* rautils.pas: no VMT offset in records
git-svn-id: branches/svenbarth/classhelpers@17150 -
the IInterface implementation to be XPCom-compatible
--- Merging r15997 through r16179 into '.':
U rtl/inc/variants.pp
U rtl/inc/objpash.inc
U rtl/inc/objpas.inc
U rtl/objpas/classes/persist.inc
U rtl/objpas/classes/compon.inc
U rtl/objpas/classes/classesh.inc
A tests/test/tconstref1.pp
A tests/test/tconstref2.pp
A tests/test/tconstref3.pp
U tests/test/tinterface4.pp
A tests/test/tconstref4.pp
U tests/webtbs/tw10897.pp
U tests/webtbs/tw4086.pp
U tests/webtbs/tw15363.pp
U tests/webtbs/tw2177.pp
U tests/webtbs/tw16592.pp
U tests/tbs/tb0546.pp
U compiler/sparc/cpupara.pas
U compiler/i386/cpupara.pas
U compiler/pdecsub.pas
U compiler/symdef.pas
U compiler/powerpc/cpupara.pas
U compiler/avr/cpupara.pas
U compiler/browcol.pas
U compiler/defcmp.pas
U compiler/powerpc64/cpupara.pas
U compiler/ncgrtti.pas
U compiler/x86_64/cpupara.pas
U compiler/opttail.pas
U compiler/htypechk.pas
U compiler/tokens.pas
U compiler/objcutil.pas
U compiler/ncal.pas
U compiler/symtable.pas
U compiler/symsym.pas
U compiler/m68k/cpupara.pas
U compiler/regvars.pas
U compiler/arm/cpupara.pas
U compiler/symconst.pas
U compiler/mips/cpupara.pas
U compiler/paramgr.pas
U compiler/psub.pas
U compiler/pdecvar.pas
U compiler/dbgstabs.pas
U compiler/options.pas
U packages/fcl-fpcunit/src/testutils.pp
git-svn-id: trunk@16180 -
be used outside the code generator
* renamed tabstractprocdef.requiredargarea into callerargareasize,
and also added calleeargareasize field; added init_paraloc_info(side)
method to init the parameter locations and init those size fields and
replaced all "if not procdef.has_paraloc_info then ..." blocks with
procdef.init_paraloc_info(callersize)"
* moved detection of stack tainting parameters from psub to
symdef/tabstractprocdef
+ added tcallparanode.contains_stack_tainting_call(), which detects
whether a parameter contains a call that makes use of stack paramters
* record for each parameter whether or not any following parameter
contains a call with stack parameters; if not, in case the current
parameter itself is a stack parameter immediately place it in its
final location also for use_fixed_stack platforms rather than
first putting it in a temporary location (part of mantis #17442)
* on use_fixed_stack platforms, always first evaluate parameters
containing a stack tainting call, since those force any preceding
stack parameters of the current call to be stored in a temp location
and copied to the final location afterwards
git-svn-id: trunk@16050 -
represent complex locations (required for full x86-64 ABI support,
which is not yet implemented) -> lots of special result handling
code has been removed and replaced by the parameter handling
routines
+ added support for composite parameters (and hence function
results) to tcg.a_load_ref_cgpara() (so it can be used for
handling, e.g., 64 bit parameters on 32 bit platforms)
* the above fixed writing past the end of allocated memory when
handling records returned in registers on x86-64 whose size is
not a multiple of 8 bytes (mantis #16357)
- removed the x86-64 and PPC specific versions of a_load_ref_cgpara(),
as they are now handled correctly by the generic version
* moved the responsibility of allocating tcgpara cpu registers
(using paramanager.allocparaloc()) from the callers of
cg.a_load*_cgpara() to the cg.a_load*_cgpara() methods
themselves (so the register allocation can be done efficiently
when dealing with function results)
* for the above, renamed paramanager.alloc/freeparaloc() to
paramanager.alloc/freecgpara(), and use paramanager.allocparaloc()
to allocate individual pcgparalocations instead
* fixed the register size of SSE2 function result registers for
x86-64 (when used for floating point), which results in removing
a few superfluous "movs? %xmm0,%xmm0" instructions
* fixed compilation of paramanagers of avr, m68k and mips after r13695
and also updated them for these new changes
git-svn-id: trunk@15350 -
-- Zusammenführen der Unterschiede zwischen Projektarchiv-URLs in ».«:
U rtl/arm/setjump.inc
A rtl/arm/thumb2.inc
U rtl/arm/divide.inc
A rtl/embedded/arm/stm32f103.pp
U rtl/inc/system.inc
U compiler/alpha/cgcpu.pas
U compiler/sparc/cgcpu.pas
U compiler/i386/cgcpu.pas
U compiler/ncgld.pas
U compiler/powerpc/cgcpu.pas
U compiler/avr/cgcpu.pas
U compiler/aggas.pas
U compiler/powerpc64/cgcpu.pas
U compiler/x86_64/cgcpu.pas
U compiler/cgobj.pas
U compiler/psystem.pas
U compiler/aasmtai.pas
U compiler/m68k/cgcpu.pas
U compiler/ncgutil.pas
U compiler/rautils.pas
U compiler/arm/raarmgas.pas
U compiler/arm/armatts.inc
U compiler/arm/cgcpu.pas
U compiler/arm/armins.dat
U compiler/arm/rgcpu.pas
U compiler/arm/cpubase.pas
U compiler/arm/agarmgas.pas
U compiler/arm/cpuinfo.pas
U compiler/arm/armop.inc
U compiler/arm/narmadd.pas
U compiler/arm/aoptcpu.pas
U compiler/arm/armatt.inc
U compiler/arm/aasmcpu.pas
U compiler/systems/t_embed.pas
U compiler/psub.pas
U compiler/options.pas
git-svn-id: trunk@13801 -
depend on that (and correct a number of cases where this was wrong)
* set the correct subreg type for xmm x86_64 parameter registers
(resolved mantis #14067)
git-svn-id: trunk@13410 -
alignment for each memory reference (mantis #12137, and
test/packages/fcl-registry/tregistry1.pp on sparc). This also
enables better code generation for packed records in many cases.
o several changes were made to the compiler to minimise the chances
of accidentally forgetting to set the alignment of memory references
in the future:
- reference_reset*() now has an extra alignment parameter
- location_reset() can now only be used for non LOC_(C)REFERENCE,
use location_reset_ref() for those (split the tloc enum so the
compiler can catch errors using range checking)
git-svn-id: trunk@12719 -
- Explicit typecasts like LongBool(byte_value) do not change ordinal value.
- Explicit typecasts like ByteBool(longint_value) do not change ordinal value and can lead to data loss if longint_value is outside of ByteBool range.
- Explicit typecasts like ByteBool(LongBool) handle type ranges correctly.
- Updated test tw10233.pp. It is passed by Delphi as well.
git-svn-id: trunk@10672 -
* Fixed sign/zero-extension in second_int_to_bool for all CPUs. x86 and pppc were not affected by this bug, but I fixed it for all CPUs for consistency.
* cg/tcnvint1 is passed on arm now.
git-svn-id: trunk@10669 -
size must happen without any mangling of the value (mantis #11027)
* moved checking for signed-to-unsigned (or vice versa) type
conversions in assignments from htypechk to ncnv (where there
was already code for similar checks) and added support for
bool_to_bool there as well
git-svn-id: trunk@10521 -
for qwordbool) + test:
o assigning true to such a variable now sets them to $ff/$ffff/$ffffffff
o these types are now all signed
o converting an integer type to a byte/word/long/qwordbool using an
explicit type cast keeps the integer's original value stored in the
bool, instead of forcing it to ord(true)/ord(false)
(mantis #10233 and #10613, implemented for all architectures, testsuite
tested for ppc32, sparc and x86)
* fixed some places where the rtl depended on longbool(true) having the
value 1
* extended several boolean tests (and adapted some to no longer assume
that byte/word/long/qwordbool(true)=1)
+ support for converting to qwordbool in second_int_to_bool for x86, ppc
and sparc
git-svn-id: trunk@9898 -
when using non-PIC references in assembler code when the compiler
is configured to generate PIC code (on ppc, sparc and arm, no
error message is given at all currently)
git-svn-id: trunk@9364 -
+ made Amiga syscalls to save/restore the frame pointer (do we really need a frame pointer?)
+ some disabled debug comments (to asm source)
+ compiler is now able to generate some VERY basic, but working Amiga-m68k executables
git-svn-id: trunk@9051 -
* small cleanups of unused variables in firstpass
* node_resources_fpu() created to get an approximation of the
required fpu registers
* for the moment use node_complexity in the CG until the
node_resource_int() is created
git-svn-id: trunk@8655 -
* fixed downsizing the precision of floating point values
* floating point constants are now treated using only the minimal
precision required (e.g. 2.0 is now a single, 1.1 extended etc)
(Delphi compatible)
git-svn-id: trunk@5927 -
from x86/aasmcpu to aasmtai and (new) aasmsym, so that when they're
finished they're available for all targets
* added dummy implementation of tai_cpu_abstract.pass1 and pass2 so there
are no more hundreds of warnings on non-x86 about constructing taicpu
instances with abstract methods
git-svn-id: trunk@5787 -
* symtables based on TFPHashObjectList and TFPObjectList
* rename torddef.typ to torddef.ordtype
* rename tfloatdef.typ to tfloatdef.floattype
* rename tdef.deftype to tdef.typ
* remove obsolete browser code, browcol is kept so the ide
can still be compiled
git-svn-id: trunk@5192 -
- fixes in asmreader, basic stuff works again, the rest is untested
- removed lot of unnecessary ungetcpuregister()s
- various other fixes i forgot
+ basic amigaos syscalls support. still lacks explicit funcretloc
git-svn-id: trunk@1943 -
getjumplabel and added type para to getlabel for specific types
* moved lineinfo generation from assemble and aggas to dbgstabs
git-svn-id: trunk@1120 -
(so both can be combined with each other, as well as with other calling
conventions)
* defined COMPPROCINLINEFIXED so SYSTEMINLINE is again activated
git-svn-id: trunk@658 -
- invalid calling conventions for a certain cpu are rejected
- arm softfloat calling conventions
- -Sp for cpu dependend code generation
- several arm fixes
- remaining code for value open array paras on heap
* fixed some volatile register bugs
+ -dnotranslation option for -dnewra, which causes the registers not to
be translated from virtual to normal registers. Requires support in
the assembler writer as well, which is only implemented in aggas/
agppcgas currently
* ppc get/freeintparaloc now check whether the parameter regs are
properly allocated/deallocated (and get an extra list para)
* ppc a_call_* now internalerrors if pi_do_call is not yet set
* fixed lot of missing pi_do_call's
* procinfo renamed to current_procinfo
* procinfo will now be stored in current_module so it can be
cleaned up properly
* gen_main_procsym changed to create_main_proc and release_main_proc
to also generate a tprocinfo structure
* fixed unit implicit initfinal
+ ret_in_reg to replace ret_in_acc
(fix some register allocation bugs at the same time)
+ save_std_register now has an extra parameter which is the
usedinproc registers
on the endianess of the host operating system -> difficult to get
right. Use lo/hi(location.valueqword) instead (remember to use
valueqword and not value!!)
+ tprocessor enumeration moved to cpuinfo
+ linker in target_info is now a class
* many many updates for m68k (will soon start to compile)
- removed some ifdef or correct them for correct cpu
* asmsymbollist global is removed and moved into a new class
tasmlibrarydata that will hold the info of a .a file which
corresponds with a single module. Added librarydata to tmodule
to keep the library info stored for the module. In the future the
objectfiles will also be stored to the tasmlibrarydata class
* all getlabel/newasmsymbol and friends are moved to the new class
