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173 Commits

Author SHA1 Message Date
florian
64e87c87bc * apply OptPass1OP to SLT/SLTU as well 2024-12-28 23:38:22 +01:00
florian
b7608b045b * RiscV: push_addr_param unified 2024-12-26 16:49:43 +01:00
florian
9ba3b12eaa * RiscV: unify push_addr_param 2024-12-25 23:33:11 +01:00
florian
065a81b72c + apply OptPass1OP to LA as well 2024-12-25 18:35:46 +01:00
florian
64ba751ef1 * make use of LA pseudo-instruction 2024-12-25 18:35:46 +01:00
florian
57da25581e + write .option pic directive if needed 2024-12-25 18:35:46 +01:00
florian
8d0bdf2f16 + RiscV: vector registers 2024-12-25 10:34:46 +01:00
florian
af233b8ef8 * RiscV: floating point registers are saved only for hard float ABIs 2024-12-25 10:16:39 +01:00
florian
49aa141703 * major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests 2024-12-22 22:37:16 +01:00
florian
4bc9f64b70 * continued unification of RiscV paramgr 2024-12-19 22:55:36 +01:00
florian
d33e7920a2 * more RiscV paramgr unification 2024-12-16 22:50:46 +01:00
florian
98b1aee2a5 * more RiscV paramgr unification 2024-12-15 23:01:55 +01:00
florian
f32eaa1564 * skeleton to unify the RiscV paramgr 
* first routines unified
 2024-12-15 15:29:05 +01:00
florian
b26c009d90 * apply Addi0Op2Op to more operations 2024-12-13 22:24:57 +01:00
florian
e8144afb6b * draft of improving Addi0Op2Op 2024-12-04 22:49:48 +01:00
florian
27a0da5a20 * typo corrected 2024-12-02 22:45:34 +01:00
florian
c45d03851a + Addi2Nop optimization 2024-12-01 11:21:09 +01:00
florian
4888442fb4 * RiscV: more reliable use_fma 2024-11-18 22:32:55 +01:00
florian
0b49fba637 + more RiscV extensions 
* make use of F and D extension flags
 2024-11-17 15:05:35 +01:00
florian
89b1cdefbe * more use of OptPass1OP 2024-11-14 22:58:37 +01:00
florian
ccae78f97a + RiscV64: apply OptPass1OP also to addiw 2024-11-13 22:56:13 +01:00
florian
1d629270ca * RiscV64: fix abs(<longint>) 2024-10-14 21:10:10 +02:00
florian
2cfb790eb7 * apply OptPass1FOP to FCVT.*.* 2024-10-13 23:18:38 +02:00
florian
c83a047dda * extend use of OptPass1FOP 2024-10-11 23:14:03 +02:00
florian
28e1daa8e1 * apply OptPass1FOP to more opcodes 2024-10-06 22:48:00 +02:00
florian
fe4f121721 * generalize FOpFsgnj02FOp optimization 2024-10-05 22:32:17 +02:00
florian
477b9ad556 + RiscV: FOp.sFsgnj.s02FOp.s optimization 2024-10-04 22:57:26 +02:00
florian
683b566cb7 * improve RiscV assembler optimizer 2024-10-03 22:56:47 +02:00
florian
42f15792ec + first batch of instructions added for Addi0Op2Op 2024-10-02 23:12:31 +02:00
florian
584e49c6a2 * Addi0Op2Op has to consider both operands 2024-10-01 22:52:43 +02:00
florian
e9fa0510d0 * RiscV: extend Addi0Op2Op 2024-09-30 22:48:18 +02:00
florian
b667be825e + RiscV: Addi0Op2Op optimization 2024-09-29 23:15:22 +02:00
florian
f356d8cc51 * fix RiscV32 compilation 2024-09-25 22:25:01 +02:00
florian
2123c59941 + RiscV: AndiAddwi02Andi optimization 2024-09-24 22:33:53 +02:00
florian
7c023d33d0 * RiscV: fix AndiAndi2Andi optimization 2024-09-24 22:21:32 +02:00
florian
8dcf4e62b7 * FCVT.W.D returns only a 32 bit int 2024-08-17 18:24:16 +02:00
florian
081af9a892 * overleft cosmetics 2024-08-13 22:54:19 +02:00
florian
6ef37d999a + Risc-V: instructions of B extension 2024-08-12 21:51:22 +02:00
florian
f1a173bdf6 * improve Risv-V optimizer 2024-08-10 21:57:55 +02:00
florian
d4816d12f7 * Risc-V 32 has also a GC variant 2024-08-08 22:58:47 +02:00
florian
1ecc880fc8 + cpu type RV64GC 2024-08-07 22:53:10 +02:00
florian
23dec631f5 + Risc-V: apply OptPass1OP to more operations 2024-08-05 22:37:59 +02:00
florian
cc2406ad74 * factor out TRVCpuAsmOptimizer.OptPass1Add 2024-08-03 21:55:41 +02:00
florian
8708144c50 + RiscV: AndiAndi2Andi 2024-08-02 22:15:37 +02:00
florian
80febbd8cf * Risc-V: use OptPass1OP more 2024-08-01 22:24:07 +02:00
florian
a4242e60b2 + Risc-V 32: apply OptPass1OP also on ADD 2024-07-28 22:56:52 +02:00
florian
657e4bf838 * more use of OptPass1OP 2024-07-28 21:39:06 +02:00
florian
9c81c4a5fa * apply OptPass1OP to more instructions 2024-07-28 16:58:49 +02:00
florian
1c96bf5d30 + S*LI x,x,0 to nop optimization 2024-07-27 21:06:49 +02:00
florian
c81f10bfbd + apply OptPass1OP also to SRL/SLL 
* fix commit
 2024-07-27 21:00:03 +02:00
florian
39f7172ee8 * do no generated debug comment in assembler output of RiscV if not requested 2024-05-25 20:16:42 +02:00
florian
a736a4bba7 + set pi_do_call on RiscV as well if we check for fpu exceptions 2024-02-16 22:48:14 +01:00
florian
a71cc71585 + function needs_check_for_fpu_exceptions to unify fpu exception handling 2024-02-13 17:42:21 +01:00
Interferon
8382c6f586 Added generic WCH32Vx RISC-V processor types using memory size suffixes 
Modified low-level startup code for RISCV32 embedded microcontrollers to
allow user code override of reset handlers for non-power-up reset events
as well as enabling user code override handlers for all 255 possible
interrupt vectors.
Separated out the low-level startup memory init into a callable procedure
to allow users that have caught reset events to init memory again if needed.

Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
 2023-08-26 22:12:00 +02:00
Pierre Muller
87e4931489 Fix fullcycle compilation error due to -Sew option 
Add 'else' branch to 'case' keyword construct
  for the setting of ABI in riscv32 assembler call.
  Do the same for riscv64 assembler call.
 2023-06-14 08:19:06 +02:00
Pierre Muller
0d256f517f Set defualt riscv32 linux abi to abi_riscv_ipl32 2023-06-13 19:39:55 +00:00
florian
0e05e908d5 riscv32-freertos: 
* unit name fixed
 * linker script fixed
 * assembler supports dwarf
 2023-02-09 21:29:06 +01:00
florian
bedd4edc72 + first work for esp32-c3 support 2023-01-28 21:28:19 +01:00
Pierre Muller
49ddf159b2 Fix internalerror generated with riscv32 compiler. 
Fix
  Compiling ./fcl-passrc/src/pscanner.pp
  pscanner.pp(2512,40) Fatal: Internal error 2006010801
  error generated for riscv32-linux target after commit #c83e6c34
  by correcting expectloc for riscv32 for 64-bit comparisons.
  Add a small test.
 2022-10-25 18:42:14 +02:00
florian
e66378ee59 * RiscV: generate mret only for FreeRTOS and Embedded 2022-07-20 22:16:19 +02:00
florian
a16f35dcb1 + support RV32E Extension 2022-07-17 22:14:13 +02:00
Jeppe
f5cf8956c5 riscv: Merge stack code, fix interrupted code 
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
 2022-07-02 15:07:42 +02:00
florian
a05aa25aad * Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738 2022-06-03 22:54:18 +02:00
florian
ea659cbc20 * "fast lane" code and comment fixed 2022-06-02 22:47:58 +02:00
florian
f1b166d6b8 * zero is a valid Risc-V register alias 2022-06-01 22:34:51 +02:00
florian
ec3a04da9b + forgotten pseudo-instructions added 2022-06-01 22:31:26 +02:00
florian
eaeb8b70ff + added Risc-V register information file generation to the compiler Makefile 
* more stringent naming of register file information for Risc-V
 2022-05-31 22:38:30 +02:00
florian
ae457a18ad * unified Risc-V 32 and 64 register data file 2022-05-30 21:10:34 +02:00
florian
4556cb35d1 + completed Risc-V 64 pseudo instructions 
* typo fixed
 2022-05-28 21:22:11 +02:00
florian
6a00f9f403 * unified Risc-V 32 and 64 cpubase.pas 2022-05-28 21:15:53 +02:00
florian
09587d0c1b * standard Risc-V pseudo instructions for Risc-V 32 completed 2022-05-28 20:47:58 +02:00
florian
b29b81ae7b * pseudo instructions for flag handling 2022-05-28 20:25:28 +02:00
pierre
c2c7982a22 Fix check that third parameter of ADDI hp1 instruction is a constant 
git-svn-id: trunk@49467 -
 2021-06-02 19:58:38 +00:00
florian
9e2bcd940a + RiscV: initial OpAddi02Op implementation 
git-svn-id: trunk@49002 -
 2021-03-18 21:49:25 +00:00
florian
9ccdf2b3bf * RiscV: unified itcpugas.pas 
git-svn-id: trunk@48960 -
 2021-03-14 10:29:23 +00:00
pierre
9775a13e02 Rough fix for riscv32 failure 
git-svn-id: trunk@48959 -
 2021-03-14 09:10:29 +00:00
florian
e047e7db91 + RiscV: initial support of pic generation 
git-svn-id: trunk@48947 -
 2021-03-13 16:18:00 +00:00
florian
d1fb44044f * unified RiscV32 and RiscV64 GAS readers 
git-svn-id: trunk@48894 -
 2021-03-07 08:53:03 +00:00
florian
6f3fccddd1 * RiscV32: properly read references with record offsets and base register 
+ RiscV32: sanity check in assembler writer

git-svn-id: trunk@48892 -
 2021-03-06 22:19:00 +00:00
florian
c15bb07bf6 * do not generate mul instructions if the mul extension is not available 
git-svn-id: trunk@48883 -
 2021-03-06 14:23:54 +00:00
pierre
01a351f804 Fix for bug report 38549 about wrong code generation 
for mips/mipsel and riscv32/riscv64 CPUs for 
  set operators '<=' and '>='.
  New tests for this bug report.
  tw38549.pp, main source, also included 
  by tw38549a.pp, tw38549b.pp, tw38459c.pp and tw38459d.pp
  with explicit {$packset X}, with X=1,2,4, or 8 added.

git-svn-id: trunk@48874 -
 2021-03-03 22:15:20 +00:00
florian
5cd4e5a016 * pass lp64d to GNU AS for abi_riscv_hf to get the right ABI set 
git-svn-id: trunk@47585 -
 2020-11-25 20:20:08 +00:00
florian
637976e83f * patch by Marģers to unify internal error numbers, resolves #37888 
git-svn-id: trunk@47103 -
 2020-10-13 19:59:01 +00:00
pierre
d4c9e1f260 Replace outdated cgop2string function by tcgsize2str function from cgbase unit to fix EXTDEBUG cycle on powerpc64le-linux 
git-svn-id: trunk@46689 -
 2020-08-25 13:29:16 +00:00
nickysn
3d81dd0b00 * ReplaceForbiddenAsmSymbolChars renamed ApplyAsmSymbolRestrictions, because now it also applies the 
label length limit

git-svn-id: branches/z80@45085 -
 2020-04-26 10:42:07 +00:00
nickysn
a8fe46c0f5 + introduced labelmaxlen in tasminfo and added code in ReplaceForbiddenAsmSymbolChars that limits the 
output label to that length

git-svn-id: branches/z80@45066 -
 2020-04-25 12:59:25 +00:00
Jeppe Johansen
2678522db5 - RISC-V: Add controller types for common RV32 MCUs. 
- Adds initial controller units for these MCUs.

Code contributed by Michael Ring

git-svn-id: trunk@43935 -
 2020-01-13 22:54:26 +00:00
Jeppe Johansen
02c3f328a2 - RISC-V: Share optimizations between 32 and 64-bit. 
git-svn-id: trunk@43934 -
 2020-01-13 22:49:23 +00:00
svenbarth
114c27fb4e * increase support for multilib binutils for RISC V by passing the ABI to the assembler 
git-svn-id: trunk@43788 -
 2019-12-25 15:23:21 +00:00
pierre
4e4f55ac0e Comparison nodes are always in LOC_REGISTER, never in LOC_JUMP for riscv32 or riscv64 CPUs 
git-svn-id: trunk@43614 -
 2019-11-29 23:28:05 +00:00
pierre
92b0ea7d02 Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors 
git-svn-id: trunk@43613 -
 2019-11-29 23:26:45 +00:00
pierre
8ea92a8280 Use correct macro to for 64-bit riscv CPU 
git-svn-id: trunk@43561 -
 2019-11-22 21:29:19 +00:00
florian
b3ed34592f + software handling of exceptions on arm 
* reworked software handling of exceptions so they can be check lazily

git-svn-id: trunk@42525 -
 2019-07-28 21:06:36 +00:00
Jonas Maebe
3fee990218 * on Mach-O, PECOFF and ELF platforms, write local symbols as hidden/ 
private_extern (or plain global in case of PECOFF, as the effect is
    the same there): visible across object files, but they become local
    when linked into a binary/library. This enables cross-unit inlining
    of functions accessig implementation-only symbols.

git-svn-id: trunk@42340 -
 2019-07-07 21:33:43 +00:00
Jeppe Johansen
a1a17447ff - Fix bug in 64bit softfloat double negation. 
- Clean up handling of CPU/FPU type handling in RISCV.
- Do more fixes to get RISCV32 working.
- Fix most soft multiplication handling for generic RISCV code. Still missing a few.
- Add RISCV embedded targets.

git-svn-id: trunk@42335 -
 2019-07-07 11:32:27 +00:00
Jonas Maebe
1b6425176b * synchronised with trunk till r42049 
git-svn-id: branches/debug_eh@42050 -
 2019-05-12 18:44:05 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 
be introduced by the next commit

git-svn-id: trunk@42046 -
 2019-05-12 14:29:03 +00:00
Jonas Maebe
a0f850d57f * synchronised with trunk till r41885 
git-svn-id: branches/debug_eh@41886 -
 2019-04-16 16:20:44 +00:00
Jeppe Johansen
2b78a8fd3d - Add support for .option directive in riscv assembler. 
- Use addiw when adjusting U32 to S32

git-svn-id: trunk@41870 -
 2019-04-14 20:51:29 +00:00
Jonas Maebe
a079e5fa80 * synchronised with trunk till r41449 
git-svn-id: branches/debug_eh@41450 -
 2019-02-24 20:01:53 +00:00