The loop checked for the wrong instruction for .opcode = A_STR. Making
the whole optimizer non functional but at least not destructive.
git-svn-id: trunk@21508 -
This optimizer folds shift/roll operations into following data
instructions.
It will change code like:
mov r0, r0, lsl #16
add r1, r0, r1
into
add r1, r1, r0, lsl #16
Source registers will be reordered when necessary, also SUB/SBC will be
replaced with RSB/RSC and vice versa when reordering is required.
It could be expanded to support more operations like LDR/STR.
git-svn-id: trunk@21507 -
This changes the ARM Peephole optimizer RedundantMovProcess to also
recognize and modify something like the following sequence.
mov r0, r1
mov r0, r0, lsl #8
this would be changed into
mov r0, r1, lsl #8
git-svn-id: trunk@21506 -
BX is supported from ARMv4T onwards, but i don't have a armv4t device to
test it.
Using BX instead of mov pc,lr allows for a better pipeline utilization
by enabling the CPUs branch predictor to work properly.
git-svn-id: trunk@21505 -
- Support MLA and MUL in DataMov2Data
- SMLAL and UMLAL are also reading from oper[0]
- UMLAL, UMULL, SMLAL and SMULL are writing to oper[1]
git-svn-id: trunk@21421 -
Reorder unaligned Load sequence on ARM
The old version produced code like that:
ldrb rDEST, [rBASE]
ldrb rTemp, [rBASE, #1]
orr rDEST, rDEST, rTEMP lsl #8 (2 stall cycles)
ldrb rTemp, [rBASE, #2]
orr rDEST, rDEST, rTEMP lsl #16 (2 stall cycles)
ldrb rTemp, [rBASE, #3]
orr rDEST, rDEST, rTEMP lsl #24 (2 stall cycles)
This creates a lot of stall-cycles on ARM Implementations with load
delay slots like Marvel Kirkwood or Intel XScale. With the usual up to 2
stall-cycles this code requires a total of 13 cycles (7 instructions + 6 stall
cycles) in best case.
The new code uses a second temp register to avoid the stall cycles.
ldrb rDEST, [rBASE]
ldrb rTemp1, [rBASE, #1]
ldrb rTemp2, [rBASE, #2]
orr rDEST, rDEST, rTEMP1 lsl #8
ldrb rTemp1, [rBASE, #3]
orr rDEST, rDEST, rTEMP2 lsl #16
orr rDEST, rDEST, rTEMP1 lsl #24 (1 stall cycle)
The rescheduling and second register bring the total cycles down to 8.
If a later rescheduling should happen for the last orr it even can go
down to 7.
git-svn-id: trunk@21363 -
Optimize ARM OP_MUL/OP_IMUL for x*ispowerof2(const+1) cases
Calculations like a*7 can be optimized to a*8-a with the usage of RSB and left
shifts which can be done in a single cycle.
git-svn-id: trunk@21351 -
Improve ARM-Peephole Optimizers
1.) Introduce a ARM-specific RegUsedAfterInstruction which analyzes
instructions and reg allocation information to see if a register is
really needed afterwards to decide if some special optimizations can be
done.
2.) Introduce "RemoveSuperfluousMove"
This tries to fold mov into a previous Data-Instruction (ADD, ORR, etc)
or LDR-Instruction.
3.) Introduce new Optimizer "DataMov2Data" and modify LdrMov2Ldr to use
RemoveSuperfluousMove
4.) Expand Ldr* and Str* Optimizers to also work on {Ldr,Str}{,b,h}
git-svn-id: trunk@21314 -
Inline a couple of small functions of the ARM-Compiler
These small changes improved overall compile times of the fpc suite by
about 2-3% running on an 1.2GHz Kirkwood.
git-svn-id: trunk@21312 -
future use by high level code generator targets
o this in turn required that all a_load*_loc* methods are called via
hlcg rather than via cg, since a location can be a subsetref/reg and
and those are no longer handled in tcg
o that then required moving several force_location_* routines into
thlcg because they use a_load_loc*, but did not take tdef size
parameters (which are required by the thlcg a_load_loc* routines)
o the only practical consequence is that from now on, you have to
use hlcg.location_force_mem/reg() (fpureg not yet) and
hlcg.gen_load_loc_cgpara() instead of the removed versions from ncgutil,
and hlcg.a_load*loc*() instead of cg.a_load*loc* if a subsetref/reg
might be involved
git-svn-id: trunk@21287 -
* Introduce MatchInstruction and MatchOperand
MatchInstruction allows to match an instruction by condition and
oppostfix. MatchOperand checks if an operand is a register and matches
another operand. In the future this could be overloaded with other
versions not only accepting TRegister.
* Optimize cmp,moveq,movne sequence on ARM
This patch implements an peephole optimizer for the following sequence:
cmp reg,const1
movne reg,const2
moveq reg,const1
* Small improvements to the ARM peephole optimizer
Most instructions in the ARM ISA have taicpu(p).oper[0]^.typ = top_reg
as the only option, so there is no need to check for it if we're
looking at those instructions.
* Remove redundant mov instructions on ARM
This is an addition to the ARM PeepHole Optimizer.
It folds code like this:
mov reg1, reg2
add reg1, reg1, (const|reg)
git-svn-id: trunk@21024 -
o support for the new codepage-aware ansistrings in the jvm branch
o empty ansistrings are now always represented by a nil pointer rather than
by an empty string, because an empty string also has a code page which
can confuse code (although this will make ansistrings harder to use
in Java code)
o more string helpers code shared between the general and jvm rtl
o support for indexbyte/word in the jvm rtl (warning: first parameter
is an open array rather than an untyped parameter there, so
indexchar(pcharvar^,10,0) will be equivalent to
indexchar[pcharvar^],10,0) there, which is different from what is
intended; changing it to an untyped parameter wouldn't help though)
o default() support is not yet complete
o calling fpcres is currently broken due to limitations in
sysutils.executeprocess() regarding handling unix quoting and
the compiler using the same command lines for scripts and directly
calling external programs
o compiling the Java compiler currently requires adding ALLOW_WARNINGS=1
to the make command line
git-svn-id: branches/jvmbackend@20887 -
of the AVR-specific ifdef'ed variant
o since the only special character we use in mangled names on all platforms
is $, added a new field to tasminfo called "dollarsign" that holds the
character $'s should be replaced with (if it doesn't have to be replaced,
leave it at $)
git-svn-id: trunk@20801 -
always points to the previous r7 on the stack (with the saved return
address coming right after it) so that the debugger and crashreporter
can use it for backtraces as specified in the ABI
o changed NR_FRAME_POINTER_REG and RS_FRAME_POINTER_REG from a symbolic
into a typed constant, and added a new method to tprocinfo that can
be used to initialze it (so it can be inited to r7/r11 depending on
the target platform)
* allow using r9 on Darwin, it was only used by the system on iOS up to
2.x, which we no longer support
* prefer using r9 and r12 before r4..r11 on Darwin, because they are
volatile and hence do not have to be saved
git-svn-id: trunk@20661 -
o new eabihf (hard float) abi
o vfpv3_d16 variant of VFP (default variant used by EABI assemblers: VFPv3
with only 16 double registers instead of 32) and pass it to GNU as
o make the odd numbered single precision floating point VFP registers
available for explicit allocation for use by the calling convention
* fixed copy/paste error in stdname of S30 register
-> use -dFPC_ARMHF to create an ARM eabi hard float compiler
(mantis #21554)
git-svn-id: trunk@20660 -
* remove unnecessary ldr after str to the same memoy location, however, to do this optimization safely, we should add support for volatile variables
git-svn-id: trunk@20399 -
* converts the embedded information into controller specific records (arm and avr)
* new cpu-specific units for several Stellaris (Fury and Tempest class) targets,
+ STM32F103RB
- old Stellaris unit has been removed
git-svn-id: trunk@18848 -
since the definition-specific adorning of JVM mangled names is Jasmin-
specific, and such code has no place in symdef
* moved code to adorn JVM mangled names for Jasmin definitions to agjasmin
git-svn-id: branches/jvmbackend@18346 -
o changed type of opsize field of tcgcasenode from tcgsize into tdef,
and fixed compilation of other code generator units after this change
git-svn-id: branches/jvmbackend@18339 -
whether the mangled name is for defining a symbol, or for referencing
it later (e.g. for a call or load of its address). The reason is that
on the JVM both cases are different.
+ jvmdef unit to encode types according to the JVM rules
+ tprocdef.jvmmangledname() to encode a procdef's JVM mangled name
(the common part of defining/referencing it; tprocdef.mangledname
afterwards adorns it as required)
git-svn-id: branches/jvmbackend@18288 -
link against Xcode 3.2.6/4-generated code for ARMv7 -- use -Cparmv7,
but note that you also have to compile the RTL and all other units with
this option for them to be linkable against other ARMv7 code when using
those tools)
git-svn-id: trunk@18069 -
* $CPU/cgcpu.pas: disable the generation of VMT loading code
* dbgstabs.pas, dbgdwarf.pas: treat virtual methods of helpers as normal methods
* ncgcal.pas: don't register virtual helper methods for WPO
* ncgrtti.pas: write virtual helper methods as normal methods to RTTI
* nobj.pas: correctly handle final and override cases in helpers
* pdecvar.pas: property getters
* rautils.pas: no VMT offset in records
git-svn-id: branches/svenbarth/classhelpers@17150 -
* generate add.w instead of add for thumb-2 in case one of the registers
is > r8
* add register interferences for the "add" instruction so the register
allocator can detect invalid instruction forms (even for assembler code)
* fixed error in thumb2.inc detected by the previous change
git-svn-id: trunk@16633 -
the IInterface implementation to be XPCom-compatible
--- Merging r15997 through r16179 into '.':
U rtl/inc/variants.pp
U rtl/inc/objpash.inc
U rtl/inc/objpas.inc
U rtl/objpas/classes/persist.inc
U rtl/objpas/classes/compon.inc
U rtl/objpas/classes/classesh.inc
A tests/test/tconstref1.pp
A tests/test/tconstref2.pp
A tests/test/tconstref3.pp
U tests/test/tinterface4.pp
A tests/test/tconstref4.pp
U tests/webtbs/tw10897.pp
U tests/webtbs/tw4086.pp
U tests/webtbs/tw15363.pp
U tests/webtbs/tw2177.pp
U tests/webtbs/tw16592.pp
U tests/tbs/tb0546.pp
U compiler/sparc/cpupara.pas
U compiler/i386/cpupara.pas
U compiler/pdecsub.pas
U compiler/symdef.pas
U compiler/powerpc/cpupara.pas
U compiler/avr/cpupara.pas
U compiler/browcol.pas
U compiler/defcmp.pas
U compiler/powerpc64/cpupara.pas
U compiler/ncgrtti.pas
U compiler/x86_64/cpupara.pas
U compiler/opttail.pas
U compiler/htypechk.pas
U compiler/tokens.pas
U compiler/objcutil.pas
U compiler/ncal.pas
U compiler/symtable.pas
U compiler/symsym.pas
U compiler/m68k/cpupara.pas
U compiler/regvars.pas
U compiler/arm/cpupara.pas
U compiler/symconst.pas
U compiler/mips/cpupara.pas
U compiler/paramgr.pas
U compiler/psub.pas
U compiler/pdecvar.pas
U compiler/dbgstabs.pas
U compiler/options.pas
U packages/fcl-fpcunit/src/testutils.pp
git-svn-id: trunk@16180 -
be used outside the code generator
* renamed tabstractprocdef.requiredargarea into callerargareasize,
and also added calleeargareasize field; added init_paraloc_info(side)
method to init the parameter locations and init those size fields and
replaced all "if not procdef.has_paraloc_info then ..." blocks with
procdef.init_paraloc_info(callersize)"
* moved detection of stack tainting parameters from psub to
symdef/tabstractprocdef
+ added tcallparanode.contains_stack_tainting_call(), which detects
whether a parameter contains a call that makes use of stack paramters
* record for each parameter whether or not any following parameter
contains a call with stack parameters; if not, in case the current
parameter itself is a stack parameter immediately place it in its
final location also for use_fixed_stack platforms rather than
first putting it in a temporary location (part of mantis #17442)
* on use_fixed_stack platforms, always first evaluate parameters
containing a stack tainting call, since those force any preceding
stack parameters of the current call to be stored in a temp location
and copied to the final location afterwards
git-svn-id: trunk@16050 -
solves the problem whereby an empty list could sometimes be inserted
after a jump table load (in case the jump table was larger than the
maximally allowed offset, and if there was a skipinstr between the
previous instruction and the jump table load) (mantis #17164)
git-svn-id: trunk@15831 -
+ support for nested procedural variables:
o activate using {$modeswitch nestedprocvars} (compatible with all
regular syntax modes, enabled by default for MacPas mode)
o activating this mode switch changes the way the frame pointer is
passed to nested routines into the same way that Delphi uses (always
passed via the stack, and if necessary removed from the stack by
the caller) -- Todo: possibly also allow using this parameter
passing convention without enabling nested procvars, maybe even
by default in Delphi mode, see mantis #9432
o both global and nested routines can be passed to/assigned to a
nested procvar (and called via them). Note that converting global
*procvars* to nested procvars is intentionally not supported, so
that this functionality can also be implemented via compile-time
generated trampolines if necessary (e.g. for LLVM or CIL backends
as long as they don't support the aforementioned parameter passing
convention)
o a nested procvar can both be declared using a Mac/ISO Pascal style
"inline" type declaration as a parameter type, or as a stand-alone
type (in the latter case, add "is nested" at the end in analogy to
"of object" for method pointers -- note that using variables of
such a type is dangerous, because if you call them once the enclosing
stack frame no longer exists on the stack, the results are
undefined; this is however allowed for Metaware Pascal compatibility)
git-svn-id: trunk@15694 -
- sort of reverted r14134, which is no longer required after the above
change (new_section() inserts the alignment itself)
* made the tai_section.create() constructor private so it cannot be
called directly anymore
git-svn-id: trunk@15482 -
* fixed record parameter passing (all records <= 4 bytes passed
by value, records > 4 bytes by reference)
* fixed procedure of object parameter passing (handle like tmethod
record) (mantis #16520)
* fixed aligning parameters for EABI (it does not depend on the
parameter size, but rather on its alignment, and also align in
case a parameter that we wanted to pass via registers has to be
passed via the stack because we ran out of registers)
git-svn-id: trunk@15390 -
represent complex locations (required for full x86-64 ABI support,
which is not yet implemented) -> lots of special result handling
code has been removed and replaced by the parameter handling
routines
+ added support for composite parameters (and hence function
results) to tcg.a_load_ref_cgpara() (so it can be used for
handling, e.g., 64 bit parameters on 32 bit platforms)
* the above fixed writing past the end of allocated memory when
handling records returned in registers on x86-64 whose size is
not a multiple of 8 bytes (mantis #16357)
- removed the x86-64 and PPC specific versions of a_load_ref_cgpara(),
as they are now handled correctly by the generic version
* moved the responsibility of allocating tcgpara cpu registers
(using paramanager.allocparaloc()) from the callers of
cg.a_load*_cgpara() to the cg.a_load*_cgpara() methods
themselves (so the register allocation can be done efficiently
when dealing with function results)
* for the above, renamed paramanager.alloc/freeparaloc() to
paramanager.alloc/freecgpara(), and use paramanager.allocparaloc()
to allocate individual pcgparalocations instead
* fixed the register size of SSE2 function result registers for
x86-64 (when used for floating point), which results in removing
a few superfluous "movs? %xmm0,%xmm0" instructions
* fixed compilation of paramanagers of avr, m68k and mips after r13695
and also updated them for these new changes
git-svn-id: trunk@15350 -
the opposite meaning, af_stabs_use_function_absolute_addresses), because it
is different on Darwin for the internal and external assembler)
git-svn-id: trunk@14342 -
and above, so this also works when calling thumb code (should actually
also be done for ARMv5T, but we don't have a monicker for that yet)
* use BX instead of "mov r15, r14" for simple returns from subroutines
on ARMv6+ to support returning to thumb code from ARM code (idem)
git-svn-id: trunk@14332 -
+ RTL support:
o VFP exceptions are disabled by default on Darwin,
because they cause kernel panics on iPhoneOS 2.2.1 at least
o all denormals are truncated to 0 on Darwin, because disabling
that also causes kernel panics on iPhoneOS 2.2.1 (probably
because otherwise denormals can also cause exceptions)
* set softfloat rounding mode correctly for non-wince/darwin/vfp
targets
+ compiler support: only half the number of single precision
registers is available due to limitations of the register
allocator
+ added a number of comments about why the stackframe on ARM is
set up the way it is by the compiler
+ added regtype and subregtype info to regsets, because they're
also used for VFP registers (+ support in assembler reader)
+ various generic support routines for dealing with floating point
values located in integer registers that have to be transferred to
mm registers (needed for VFP)
* renamed use_sse() to use_vectorfpu() and also use it for
ARM/vfp support
o only superficially tested for Linux (compiler compiled with -Cpvfpv6
-Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least
the fpu exception handler still needs to be implemented), Darwin has
been tested more thoroughly
+ added ARMv6 cpu type and made it default for Darwin/ARM
+ ARMv6+ implementations of atomic operations using ldrex/strex
* don't use r9 on Darwin/ARM, as it's reserved under certain
circumstances (don't know yet which ones)
* changed C-test object files for ARM/Darwin to ARMv6 versions
* check in assembler reader that regsets are not empty, because
instructions with a regset operand have undefined behaviour in that
case
* fixed resultdef of tarmtypeconvnode.first_int_to_real in case of
int64->single type conversion
* fixed constant pool locations in case 64 bit constants are generated,
and/or when vfp instructions with limited reach are present
WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all
code with -Cparmv6 (or higher), or you will get crashes. The reason is
that storing/restoring multiple VFP registers must happen using
different instructions on pre/post-ARMv6.
git-svn-id: trunk@14317 -
-- Zusammenführen der Unterschiede zwischen Projektarchiv-URLs in ».«:
U rtl/arm/setjump.inc
A rtl/arm/thumb2.inc
U rtl/arm/divide.inc
A rtl/embedded/arm/stm32f103.pp
U rtl/inc/system.inc
U compiler/alpha/cgcpu.pas
U compiler/sparc/cgcpu.pas
U compiler/i386/cgcpu.pas
U compiler/ncgld.pas
U compiler/powerpc/cgcpu.pas
U compiler/avr/cgcpu.pas
U compiler/aggas.pas
U compiler/powerpc64/cgcpu.pas
U compiler/x86_64/cgcpu.pas
U compiler/cgobj.pas
U compiler/psystem.pas
U compiler/aasmtai.pas
U compiler/m68k/cgcpu.pas
U compiler/ncgutil.pas
U compiler/rautils.pas
U compiler/arm/raarmgas.pas
U compiler/arm/armatts.inc
U compiler/arm/cgcpu.pas
U compiler/arm/armins.dat
U compiler/arm/rgcpu.pas
U compiler/arm/cpubase.pas
U compiler/arm/agarmgas.pas
U compiler/arm/cpuinfo.pas
U compiler/arm/armop.inc
U compiler/arm/narmadd.pas
U compiler/arm/aoptcpu.pas
U compiler/arm/armatt.inc
U compiler/arm/aasmcpu.pas
U compiler/systems/t_embed.pas
U compiler/psub.pas
U compiler/options.pas
git-svn-id: trunk@13801 -
* the objc unit links against the Foundation instead of against the Cocoa
framework, and inludes an interface to either the fragile or non-fragile
obj-c run time depending on the target platform
+ support for the non-fragile Objective-C runtime/ABI, as used on Mac OS X
for ARM (iPhone) 64 bit (PowerPC/64, x86_64) -- all these targets now
are now also supported for the objectivec1 modeswitch
+ support for private_extern symbol bindings, required for the above
* mark objcclasses that are declared in the implementation section of a
unit as "hidden" (not sure what the effect is, since the Objective-C
runtime does not seem to do anything with this flag)
* enabled all obj-c tests for the newly supported platforms
git-svn-id: branches/objc@13763 -
forced to something else by the compiler (internal rtl functions etc),
necessary for the objc branch
* fixed adding all used function result registers to the list of
registers that may need to be saved before a function call
git-svn-id: trunk@13695 -
depend on that (and correct a number of cases where this was wrong)
* set the correct subreg type for xmm x86_64 parameter registers
(resolved mantis #14067)
git-svn-id: trunk@13410 -
alignment for each memory reference (mantis #12137, and
test/packages/fcl-registry/tregistry1.pp on sparc). This also
enables better code generation for packed records in many cases.
o several changes were made to the compiler to minimise the chances
of accidentally forgetting to set the alignment of memory references
in the future:
- reference_reset*() now has an extra alignment parameter
- location_reset() can now only be used for non LOC_(C)REFERENCE,
use location_reset_ref() for those (split the tloc enum so the
compiler can catch errors using range checking)
git-svn-id: trunk@12719 -
the syntax is exactly the same as for "external", except for
the keyword. It is currently only active for Darwin targets.
It should also work at least for Linux targets, but only with
the GNU assembler (which is why it is not activated there)
+ test for this functionality
git-svn-id: trunk@12009 -
+ write the header for non-pic darwin/arm call stubs properly in aggas
* r9 is not available for general use on darwin/arm according to the llvm
code generator
git-svn-id: trunk@11862 -
method in TArmGNUAssembler, because it's cleaner (no ifdef) and it
mustn't be added for darwin (which uses TArmAppleGNUAssembler)
git-svn-id: trunk@11854 -
* Suppressed 2 unreachable code warnings.
* Now x86 compiler compiles without warnings and notes! It will be great to keep such state in future...
git-svn-id: trunk@11455 -
