to free up space for more ait_* types in taitype (can't have
more than 32 because they have to fit in a small set)
o factored out writing of floating point numbers as an array of
byte in the external assemblers
git-svn-id: branches/hlcgllvm@28105 -
* Change register type of second operand in CTC1 and CFC1 instructions to R_SPECIALREGISTER, so it is not output using a symbolic name. Mantis #26380.
git-svn-id: trunk@28034 -
While it can be correct from some point of view, it does not prevent aliasing a single-precision register into upper half of double-precision one. This is currently handled by making only even floating-point registers available to RA. At the same time, it somehow (possibly due to another bug in RA) generates a lot of unnecessary moves, as if physical double-precision registers conflict with each other. Anyway, removing it considerably improves the code without regressions in the test suite.
git-svn-id: trunk@27999 -
* cpubase.pas, std_regname: changed logic to lookup known names for special registers before resorting to default name, so that $fcc0..$fcc7 can be used as operands.
git-svn-id: trunk@27992 -
The code generator gets two new methods, a_mul_reg_reg_pair and g_div_const_reg_reg. The first one is basically 32x32 to 64 bits multiplication (or any other size, with result having twice the size of arguments), which must be implemented for every target. The second one actually does the job, its default implementation taken from powerpc64 and is sufficiently good for all three-address targets.
+ Enabled optimized division for MIPS target, target-specific changes are under 30 lines.
git-svn-id: trunk@27904 -
o made all (non-abstract) tdef and tsym constructors virtual
o added c*def/c*sym classref types for every (non-abstract) t*def/t*sym
class
o added cpusym unit for every architecture that derives a tcpu*def/tcpu*sym
class from the base classes, and initialises the c*def/c*sym classes with
them. This is done so that the llvm target will be able to derive from
the tcpu*def/sym classes without umpteen ifdefs, and it also means that
the WPO can devirtualise everything because the c* variables are only
initialised with one class type
o replaced all t*def/t*sym constructor calls with c*def/c*sym constructor
calls
git-svn-id: trunk@27361 -
required for the LLVM support (LLVM parameter support is not yet
included)
* always return the function return loc from a_call*, again as required
for the LLVM support
git-svn-id: branches/hlcgllvm@26992 -
* Change MIPS jump tables in PIC mode to use gp-relative constants, making them ABI-compliant and not requiring dynamic relocations.
git-svn-id: trunk@26886 -
do_spill_replace routines, will be necessary by llvm register
allocator to determine the tdef corresponding to that register
* replaced uses of taicpu with tai_cpu_abstract_sym in the register
allocator so that it can work both with taicpu and taillvm instructions
git-svn-id: branches/hlcgllvm@26043 -
cgobj.pas, tcg:
* g_save_registers: add the amount of used address registers to size as well
* g_save_registers: save all used address registers
* g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
* rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
* add a saved_address_registers variable with one entry of RS_INVALID
At least a "make fullcycle" did complete.
git-svn-id: trunk@25664 -
* Deallocate GP save temp in epilogue to avoid warnings when compiled with -dEXTDEBUG
* g_concatcopy: don't check alignment, this allows single byte or word locations to be copied with 2 instructions. Larger unaligned references are supposed to be handled in g_concatcopy_unaligned instead.
git-svn-id: trunk@25147 -
* Use fpc_[int64|qword]_to_double instead of [int64|qword]_to_float64, makes RTL no longer dependent on softfloat code.
* Move 32-bit values from integer registers to FPU registers without using memory.
* Fixed branching, was still using a macro and delay slot was missing.
git-svn-id: trunk@25071 -
The difference in branch instruction formats is isolated in function JumpTargetOp, it is a plain function rather than a virtual method, so it can be easily inlined and, after inlining, produces the same code for non-MIPS targets as it was before change.
git-svn-id: trunk@25033 -
* Moved jump tables into data segment. For disassembly-based stack unwinding to work properly, MIPS ABI expects text segment to contain instructions only.
git-svn-id: trunk@24904 -
+ Implemented subset of "spill replace" functionality, replacing moves from/to spilled registers with loads/stores to spill locations. This helps to reduce amount of instructions.
git-svn-id: trunk@24900 -
* Output registers of type R_SPECIALREGISTER as numbers.
+ For MTC0/MFC0 instructions, set type of first operand to R_SPECIALREGISTER, since it designates a coprocessor register.
git-svn-id: trunk@24799 -
contains the tcgsize of the entire parameter rather than only of
what is left (-> calculate it from the remaining parameter length)
git-svn-id: trunk@24776 -
- removed mips_cpu variable and cpu_mips_default CPU type.
* globals.pas: default CPU type changed to MIPS2, this is what was passed to assembler before.
git-svn-id: trunk@24643 -
- references cannot be in brackets
- registers are only prefixed by dollar, never by percent
- syntax x@LO is not supported, must be %lo(x).
git-svn-id: trunk@24633 -
* reworked condition codes, changed BC1T and BC1F from separate instructions to condition jumps.
- removed A_P_SW, A_P_LW and A_SPARC8UNIMP
+ support '.set at' and '.set noat' directives
+ prepare to support bgtz,bgez,bltz,blez instructions.
git-svn-id: trunk@24631 -
+ Implemented overflow checking for unsigned 32-bit addition and subtraction.
* Use optimize_op_const instead of custom optimizations.
* Change AND/OR/XOR into ANDI/ORI/XORI if they use immediate operands, and use correct range for these immediate operands, must be 0..65535 unlike -32768..32767 for arithmetic operations.
* Don't treat AND/OR/XOR as macros, no longer necessary.
* Don't treat BEQ/BNE as macros either.
git-svn-id: trunk@24445 -
* TCGMIPS.a_load_reg_reg: generate CPU instructions instead of macros
* TCGMIPS.a_cmp_const_reg_label: load constant using a_load_const_reg instead of LI macro (it may also end up with LI, but tries to optimize when possible).
- removed unused variables.
git-svn-id: trunk@24418 -
* shorter by 280 lines
* generates actual instructions instead of macros
* uses immediate operands for constants when possible
* 64-bit and float comparisons use LOC_JUMP as location
git-svn-id: trunk@24236 -
- Removed TMIPSProcInfo.needs_frame_pointer, it duplicates pi_needs_stackframe flag.
- Don't save RA for leaf procedures.
* GP is caller-saved register, it does not need saving/restoring as nonvolatile registers. Handle its restore position as a "normal" temp, whose offset is known before secondpass. This allows to handle PIC calls without involving GAS macro processing.
git-svn-id: trunk@23885 -
+ Favor 'weak' parameter in a_call_name of both thlcgmips and TCGMIPS.
* make_simple_ref and a_loadaddr_ref_reg: require input references to be 'raw' (no refaddr=addr_pic, etc) and do not use GP as base/index. If it's not true, raise an internal error. When addr_pic_call16 or so needs to be generated, it must be done without calling the mentioned methods.
* thlcgmips.a_call_name: generate PIC sequence for procedures declared as 'external', instead of 'cdecl', this is more correct because ABI has only one calling convention.
- make_simple_ref_fpu removed, there's no reason to handle references to floating-point data in different way.
- a_loadaddr_ref_cgpara override also removed, generic method does the job just well.
- thlcgmips.a_call_ref and a_call_reg overrides removed because indirect calls are now always done using $t9.
git-svn-id: trunk@23698 -
* Abort if attempting to emit a call without pi_do_call flag set, because the outgoing parameter area determines layout of temps and therefore cannot be created/changed during pass 2.
* Bypass g_concatcopy_move if procedure is a leaf one, due to the restriction mentioned above.
git-svn-id: trunk@23644 -
* Parameters passed in registers are no longer forced to stack, therefore assembler routines using 'lw' instruction to load such parameters must have it changed to 'move' (tb0072.pp).
git-svn-id: trunk@23627 -
* Also changed parameter management to allocate a single LOC_REFERENCE location for any parameter (or part of a parameter) passed on stack. Such locations can now be handled by generic code. As a consequence, TGMIPS.a_load_const_cgpara and a_load_ref_cgpara methods are no longer necessary (moreover they were ignoring parameter shifting).
* a_loadfpu_ref_cgpara patched to handle 64-bit location, which are now possible.
* This change eliminates code generation madness where each word of a record was copied individually, thus passing by value a 32K-word sized record was bloating into 64K instructions, multiply this number by 2 for larger records due to limited immediate offsets, and by another 2 for global record in PIC mode :/
git-svn-id: trunk@23575 -
* cpugas.pas: GetReferenceString: rewritten, it is easier than trying to fix it. Fixes incorrect writing of non-PIC references containing base, symbol and offset together, and some forms of PIC references. Also supports newly introduced address types.
git-svn-id: trunk@23555 -
* Reused applicable code from the above mentioned method in tMIPSELnotnode.second_boolean, it is more efficient in handling 64-bit data.
git-svn-id: trunk@23531 -
- removed a_jmp_cond, it's not virtual and not applicable to this CPU.
* a_loadfpu_reg_cgpara: use direct register moves for simple destinations.
* g_concatcopy: don't take address of source/destination for small amounts of data if possible, for single 32-bit moves this reduces number of generated instructions from 4 to 2.
* g_intf_wrapper: 'Self' is in R4 (a0), not R2. Fixes test/tinterface1.pp.
* mips/cpupara.pas: for functions with result returned in parameter, pass its address in a0 only if result is a record. ABI does not specify behavior for types except records/unions. At the same time, Pascal code relies on the fact that results like strings/interfaces does not change their locations, i.e. "function foo(<self>): IInterface" can be invoked as "procedure foo(<self>, out obj)". This fixes test/tdel1.pp and some Variant-related tests.
git-svn-id: trunk@23377 -
ARM status: roughly corresponds to i386 one, passes the test suite. Handles libraries, can link static libc code including basic PIC and TLS IE/LE stuff. Completely misses Thumb support. Also does not handle ABI-specific stuff, for this reason internally linked .so cannot be used for linking executables with ld. Little-endian only. Tested only on "versatilepb" QEMU virtual machine.
MIPS status: can link the compiler and at least some dynamic executables including fpmake. Some PIC support is present but almost untested. Specific header flags and sections are also not handled yet. Written to handle both endian, but tested for big-endian only ("malta" QEMU VM), including cross-linking from x86_64.
git-svn-id: trunk@23376 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.
r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.
git-svn-id: trunk@22817 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
like field reordering (possible problems cracker classes) or using ebp as normal register (broken
stack traces from dump_stack)
+ niln is also valid in a cse domain
* parameters passed by reference shall have a complexity >1
* load nodes from outer scopes shall have a complexity >1
* better cse debugging
+ more node types added to cse
* consider parameters passed by reference in cse
* take care of cse in parameters in simple cases
git-svn-id: trunk@22050 -
order to minimise memory losses due to alignment padding. Not yet enabled
by default at any optimization level, but can be (de)activated separately
via -Oo(no)orderfields
o added separate tdef.structalignment method that returns the alignment
of a type when it appears in a record/object/class (factors out
AIX-specific double alignment in structs)
o changed the handling of the offset of a delegate interface
implemented via a field, by taking the field offset on demand
rather than at declaration time (because the ordering optimization
causes the offsets of fields to be unknown until the entire
declaration has been parsed)
git-svn-id: trunk@21947 -
used across multiple levels of inheritance such as on MIPS (and the code
has to be reusable for a_call_ref/reeg in the future anyway)
git-svn-id: trunk@21906 -
result location (NR_FUNCTION_RESULT_REG is not valid on all platforms)
o this requires passing the forced function result type (if any) to this
method
o a generic, basic thlcg.a_call_name() is now available that sets the
function result location; can be called by descendants
* the availability under all circumstances of the correct function return
type enables g_call_system_proc() on the JVM platform to now determine
by itself how many stack slots are removed by the call -> do so, instead
of manually counting them (or forgetting to do so and messing up the
maximum evaluation stack height calculations)
git-svn-id: trunk@21862 -
psub.pas: Use new fpc_compiler_has_fixup_jmps conditional.
mips/aasmcpu.pas: MIPS specific fixup_jmps function,
The insttruction distance calculation is not exact as
some pseudo-instruction can be expanded to a variable number of real instructions
real calculation would only be possible if we first
convert pseudo-instuctions to real instructions before calling fixup_jmps.
ncgutil.pas: Revert commit r21791
ncgcon.pas: Revert commit r21786
mips/cgcpu.pas: Partial revert of commit r21798, no need to always use A_J,
as fixup_jmps now handles out of range branches.
git-svn-id: trunk@21822 -
