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1022 Commits

Author SHA1 Message Date
Jeppe Johansen
387824c1ee Added some APSR register bitmask definitions. 
Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions.
Fixed emission of regsets of S and D registers above 15.
Fixed assembler reader for RRX shiftmode.
There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader.

git-svn-id: branches/laksen/armiw@29277 -
 2014-12-12 22:23:44 +00:00
Jeppe Johansen
414bfba2b2 Emitted instruction was B instead of BL for BL/BLX. 
git-svn-id: branches/laksen/armiw@29262 -
 2014-12-11 22:11:10 +00:00
Jeppe Johansen
e8cb1e198d Forgot to rebuild instruction tables. 
git-svn-id: branches/laksen/armiw@29261 -
 2014-12-11 21:58:05 +00:00
Jeppe Johansen
0b5bcdf439 Modify fixup of BL/BLX instructions and ensure proper form is generated. 
git-svn-id: branches/laksen/armiw@29260 -
 2014-12-11 21:50:44 +00:00
Jeppe Johansen
284a4d9dd7 Encoding of preindexed LDRH/STRH opcodes was missing. 
git-svn-id: branches/laksen/armiw@29254 -
 2014-12-11 11:20:25 +00:00
Jeppe Johansen
b5cd9c048e Small fix for uninitialized variables causing warnings. 
git-svn-id: branches/laksen/armiw@29253 -
 2014-12-11 09:26:48 +00:00
Jeppe Johansen
eb3eaab54b Fix some small encoding bugs. 
git-svn-id: branches/laksen/armiw@29250 -
 2014-12-10 23:28:09 +00:00
Jeppe Johansen
9e5979e8be Implemented UAL syntax support in the ARM assembler reader. Can be toggled with a field for now, but not implemented yet. Still using pre-UAL syntax for now. 
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax.
Updated VFP code in RTL to use UAL syntax too.
Added preliminary ELF support for ARM.
Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target.

git-svn-id: branches/laksen/armiw@29247 -
 2014-12-10 20:44:34 +00:00
Jeppe Johansen
d023c63ad0 Add a lot of instruction table entries and missing instructions for support of most ARM32 mode instructions from ARMv4 up ARMv7A. 
Add some VFP registers.
Rebuilt tables.
Added a lot of VFPv3 and Advanced SIMD(not supported yet) oppostfixes.
Implemented code in aasmcpu to generate binary code from the instructions. Only ARM32 supported so far.

git-svn-id: branches/laksen/armiw@29246 -
 2014-12-10 20:38:23 +00:00
Jeppe Johansen
3bc1db9612 Fixed breakage in the ARM peephole optimizer indirectly brought to light by r29189. 
git-svn-id: trunk@29191 -
 2014-12-01 14:39:40 +00:00
Jeppe Johansen
d04e988ff1 Make sure optimizer don't generate invalid assembler forms (LDRD and STRD). 
git-svn-id: trunk@29189 -
 2014-11-30 17:34:37 +00:00
florian
5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, 
this is an exact operation so it is always allowed
* change only divisions by normal numbers into multiplications

git-svn-id: trunk@29085 -
 2014-11-16 20:47:38 +00:00
Tomas Hajny
3ee3542744 * boolean constant instead of IFDEFs for detection of microcontroller support 
git-svn-id: trunk@29052 -
 2014-11-10 12:34:59 +00:00
Jeppe Johansen
d3e91bb60c Fixed issue #26965. The peephole optimization didn't move a potential register deallocation to after the ldr instruction causing mov's to be removed. 
git-svn-id: trunk@28977 -
 2014-11-03 18:33:32 +00:00
sergei
a3c439c60f - No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up. 
A more radical approach is to remove them altogether. Tested with i386-win32 (the oldest peephole optimizer), mips-linux (the newest one) and arm-linux (the most complex one) targets. The fallout was limited to two minor issues fixed in r28629 and r28708, respectively.

git-svn-id: trunk@28711 -
 2014-09-22 21:33:50 +00:00
sergei
d37e72dbf9 * ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions. 
git-svn-id: trunk@28708 -
 2014-09-22 16:18:16 +00:00
sergei
b08ffa0a87 * ARM: fixed detecting Thumb-style jump tables in insertpcrelativedata() after r28546. 
git-svn-id: trunk@28702 -
 2014-09-21 01:59:25 +00:00
sergei
4a90d7e3de + ARM internal linker: very initial support for Thumb mode, helloworld-class programs compiled with "-Cparmv6m -CIthumb" can now run. 
git-svn-id: trunk@28697 -
 2014-09-19 22:33:37 +00:00
Károly Balogh
1b0a1f4508 ARM: mimic what GNU C does while calling the profiling mcount on ARM 
git-svn-id: trunk@28648 -
 2014-09-13 00:17:10 +00:00
Károly Balogh
739c66291d ARM: first naive attempt to get gprofiling work for arm-linux. (Work-In-Progress, but at least for me it doesn't explode) 
git-svn-id: trunk@28645 -
 2014-09-12 18:51:02 +00:00
florian
3f71b059e5 * improve ldr*/str* handling for arm thumb 
git-svn-id: trunk@28583 -
 2014-09-02 19:37:45 +00:00
florian
2fa7171a45 * generate AND for small set comparisons also when only set vars are involved using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28569 -
 2014-08-31 20:43:13 +00:00
florian
8a7c16327c * fixes reference handling for arm thumb and ldrh, not perfect yet 
git-svn-id: trunk@28568 -
 2014-08-31 18:00:10 +00:00
florian
81c717fc06 + implemented tthumbcgarm.g_external_wrapper in a way which does not destroy lr 
git-svn-id: trunk@28560 -
 2014-08-31 16:35:01 +00:00
florian
dffdde7d53 * fixes reference handling for arm thumb and ldrb, not perfect yet and other ldr/str types might need similiar fixes 
git-svn-id: trunk@28549 -
 2014-08-31 11:37:17 +00:00
florian
db01c50a4f * fixes jump table generate for arm thumb 
git-svn-id: trunk@28546 -
 2014-08-30 22:13:09 +00:00
florian
836a6e46ca * several issues with interface wrappers for thumb fixed 
git-svn-id: trunk@28542 -
 2014-08-30 20:38:26 +00:00
florian
97fc823e33 * generate AND for small set comparions using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28540 -
 2014-08-30 18:02:59 +00:00
florian
09728a9ae2 * improved r28534: LDR/STR on thumb do not support registers >r7 as destination/source 
git-svn-id: trunk@28538 -
 2014-08-30 12:13:00 +00:00
Károly Balogh
5a7b1f00cf ARM: Thumb is an ugly mess, but this at least makes fcl-image package to build with -Ooregvar. someone with more clue is welcomed to review and come up with a better patch. 
git-svn-id: trunk@28534 -
 2014-08-29 17:04:48 +00:00
Károly Balogh
09608a1c28 * fix warnings when compiling the compiler with DFA optimizer enabled on ARM 
git-svn-id: trunk@28498 -
 2014-08-20 13:16:58 +00:00
Jonas Maebe
b18ba8e85b * syncrhonised with trunk up till r28471 
git-svn-id: branches/hlcgllvm@28495 -
 2014-08-19 20:23:11 +00:00
Jonas Maebe
b745dcc64c * moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because 
for some platforms it depends on that routine

git-svn-id: branches/hlcgllvm@28492 -
 2014-08-19 20:22:54 +00:00
Jonas Maebe
e21d31dc99 * fixed compilation with range checking enabled 
git-svn-id: trunk@28447 -
 2014-08-18 20:06:27 +00:00
Jonas Maebe
5c75b6dd6b * synchronised with trunk up till r28402 
git-svn-id: branches/hlcgllvm@28403 -
 2014-08-13 16:04:30 +00:00
Jonas Maebe
c6ddf0001c * simplified in_smallset() and removed some old cruft (there's no need 
anymore to change the register size)

git-svn-id: branches/hlcgllvm@28400 -
 2014-08-12 23:17:45 +00:00
Jonas Maebe
5e280b3131 * don't convert movs into (the non-existing) ldrs in do_spill_replace() 
git-svn-id: trunk@28390 -
 2014-08-12 20:14:24 +00:00
masta
96915b3f0c 16bit Thumb is not able to use tst with an immediate value 
r28315 introduced an arm optimization which requires
  tst rX, #imm
to work. This is not available on 16bit thumb, I've disabled that
optimization on thumb for now.

git-svn-id: trunk@28360 -
 2014-08-10 15:30:44 +00:00
masta
7e22bd53b6 Changed ARMs StrLdr2StrMov peephole optimizer look further ahead 
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.

git-svn-id: trunk@28344 -
 2014-08-08 15:31:10 +00:00
masta
bfa85218fa Introduce TCpuAsmOptimizer.GetNextInstructionUsingRef 
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.

git-svn-id: trunk@28343 -
 2014-08-08 15:31:06 +00:00
masta
d1c5f89976 Make Next an Out-parameter in ARMs GetNextInstructionUsingReg 
The input to Next is not used, reflect that properly.

git-svn-id: trunk@28342 -
 2014-08-08 15:31:01 +00:00
masta
b898b169d4 Fixed 0-cmp optimization in tarmaddnode.second_cmp64bit 
Commit r28315 prevented "= 0" compare-optimizations. Should be fixed now.

git-svn-id: trunk@28317 -
 2014-08-06 15:01:24 +00:00
masta
c88fdb6a4a Add minor optimization for int64 < 0 on arm 
This is a very common construct in normal code and also heavily used in
softfpu code.

The ARM-cg will now just test for the MSB of reghi to be set, instead of
a full comparison against constant 0.

git-svn-id: trunk@28315 -
 2014-08-05 21:31:20 +00:00
masta
7a0c79de60 Fix for AndLsl2Lsl in ARM Peephole optimizer 
AndLsl2Lsl assigned the wrong register to the remaining instruction, and
also did not check for the register.

git-svn-id: trunk@28285 -
 2014-07-31 23:09:33 +00:00
masta
85d208fea4 Fix ARM LoadScheduler in case of Pre/PostIndexed addressing 
There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.

ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2

got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2

and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1

Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1

so r1 got loaded from a modified base-register.

This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.

git-svn-id: trunk@28284 -
 2014-07-31 19:57:09 +00:00
sergei
e4fea2ebc8 * Dummy implementations of a_bit_scan_reg_reg and g_stackpointer_alloc in tcg, removes the need to override these methods in every descendant code generator solely to avoid "constructing a class with abstract method" warning. 
git-svn-id: trunk@28175 -
 2014-07-06 11:34:04 +00:00
Jonas Maebe
7949bebb8d * synchronised with r28168 of trunk 
git-svn-id: branches/hlcgllvm@28169 -
 2014-07-05 21:30:28 +00:00
Jonas Maebe
1516661249 + new chlcgobj class reference variable that can be used to call thlcg* 
virtual methods even when hlcg doesn't contain a valid instance

git-svn-id: branches/hlcgllvm@28143 -
 2014-07-03 22:28:31 +00:00
Jonas Maebe
b0ff41406a * grouped all tai_real* types into a single tai_realconst type, 
to free up space for more ait_* types in taitype (can't have
    more than 32 because they have to fit in a small set)
   o factored out writing of floating point numbers as an array of
     byte in the external assemblers

git-svn-id: branches/hlcgllvm@28105 -
 2014-07-01 16:29:58 +00:00
Jeppe Johansen
857a849173 Added an additional check to the MulAdd2MLA optimization. The operands of the multiplication weren't checked. 
git-svn-id: trunk@28071 -
 2014-06-26 06:05:08 +00:00
Jeppe Johansen
a1197460e1 Constrained a number of optimizations and updated reference offsets for ARM Thumb. 
Embedded target can now build with optimizations.

git-svn-id: trunk@28023 -
 2014-06-21 13:26:33 +00:00
Jeppe Johansen
0dc39b5d63 Applied patch from Michael Ring that adds some startup code for some new stm32f0 and stm32f1 controllers, and fixes naming on some LPC ARMv6m controllers. 
git-svn-id: trunk@28009 -
 2014-06-20 06:49:04 +00:00
masta
0cb1a129b3 {ARM} Implement usage of generic division-by-const optimization 
This utilizes the code commited in r27904 to convert a division by const
into a 32x32->64 bit multiplication for ARM.

git-svn-id: trunk@27929 -
 2014-06-10 20:49:18 +00:00
Jeppe Johansen
96b73b0076 Fixed generation of abs calls for thumb and thumb-2 targets. 
git-svn-id: trunk@27926 -
 2014-06-10 17:48:09 +00:00
Károly Balogh
af95876eba arm: an attempt to improve the a_op_const_ref patch in r27881 
git-svn-id: trunk@27882 -
 2014-06-06 20:48:31 +00:00
Károly Balogh
5b262df7d0 arm: have a CPU specific op_const_ref, so the reference doesn't get fixed up both in a_load_reg_ref and a_load_ref_reg 
git-svn-id: trunk@27881 -
 2014-06-06 17:44:45 +00:00
Jonas Maebe
bacd303208 * synchronized with trunk up to r27758 
git-svn-id: branches/hlcgllvm@27779 -
 2014-05-12 16:12:34 +00:00
sergei
196436b7e7 * ARM: Test if range check of floating point constants is necessary in the same way as on other targets. This should have been part of r10940 6 years ago... 
git-svn-id: trunk@27630 -
 2014-04-22 06:51:54 +00:00
sergei
819f6de01a * ARM: fixed floating point comparison flags for VFP hardfloat (part of Mantis #9362). 
git-svn-id: trunk@27611 -
 2014-04-20 17:06:32 +00:00
sergei
4c3a4646ec * Fixed floating-point comparisons for softfloat targets (part of Mantis #9362). 
git-svn-id: trunk@27584 -
 2014-04-15 23:36:21 +00:00
svenbarth
02495c17bd Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym". 
git-svn-id: trunk@27531 -
 2014-04-11 14:30:59 +00:00
sergei
eeb15fc445 * Added virtual method tprocinfo.postprocess_code and moved target-specific processing from base class into target-specific descendant classes (ARM and AVR, other targets still to do). 
git-svn-id: trunk@27449 -
 2014-04-02 13:14:06 +00:00
Jonas Maebe
d452686c39 * moved pbestrealtype from symdef to symcpu 
git-svn-id: trunk@27441 -
 2014-04-01 21:41:37 +00:00
Jonas Maebe
5053a39501 * moved ARM-specific tprocdef.total_stackframe_size field to cpu-specific 
descendant

git-svn-id: trunk@27437 -
 2014-04-01 21:41:24 +00:00
sergei
68b97bee5a * ARM: Implemented floating-point negation and abs() for softfloat using integer instructions. Fixes webtbs/tw4534.pp, and also yields much faster code than existing implementation. 
Background: these operations are defined as flipping or clearing the upper bit of number, respectively, and never result in precision loss or raise floating-point exceptions.

git-svn-id: trunk@27411 -
 2014-03-31 15:03:15 +00:00
Jonas Maebe
dae5d1ff62 + added class reference types of the architecture-specific t*def/t*sym 
classes

git-svn-id: trunk@27396 -
 2014-03-30 21:04:32 +00:00
florian
8dfcc2b399 * do not reuse tmp. registers in tbasecgarm.handle_load_store 
git-svn-id: trunk@27387 -
 2014-03-30 17:28:45 +00:00
Jonas Maebe
b57c95043f + support overriding tdef/tsym methods with target-specific functionality: 
o made all (non-abstract) tdef and tsym constructors virtual
   o added c*def/c*sym classref types for every (non-abstract) t*def/t*sym
     class
   o added cpusym unit for every architecture that derives a tcpu*def/tcpu*sym
     class from the base classes, and initialises the c*def/c*sym classes with
     them. This is done so that the llvm target will be able to derive from
     the tcpu*def/sym classes without umpteen ifdefs, and it also means that
     the WPO can devirtualise everything because the c* variables are only
     initialised with one class type
   o replaced all t*def/t*sym constructor calls with c*def/c*sym constructor
     calls

git-svn-id: trunk@27361 -
 2014-03-29 22:31:55 +00:00
florian
9464dad2b4 * handle vldr/vstr references with offsets correctly 
git-svn-id: trunk@27273 -
 2014-03-24 19:20:29 +00:00
florian
01b311f6cf * do not insert constant tables on arm thumb in it* sequences 
git-svn-id: trunk@27272 -
 2014-03-24 19:20:01 +00:00
florian
3309254474 * do not write a space before the condition for instructions without operands, not sure why this was there 
git-svn-id: trunk@27268 -
 2014-03-24 17:09:28 +00:00
florian
23c8517418 * applying opXYX2opsXY to ADD makes no sense on thumb-2 (at least as far as I can see) 
git-svn-id: trunk@27267 -
 2014-03-24 17:01:38 +00:00
florian
686a2d2f3f + Support omitting the frame pointer on arm even in procedures with incoming parameters 
on the stack, this can be enabled by -OoFORCENOSTACKFRAME. This reduces the required
  entry/exit code and makes an extra register available to the compiler. However, since this is
  based on an estimation of the required stack size, it might have two drawbacks:
  either the stack frame is estimated to big, the program requires a bigger stack than needed
  or it is estimated too small, then the compiler throws an internalerror during compilation. These
  issues can be overcome as soon as the compiler supports recompiling subroutines if needed.

git-svn-id: trunk@27239 -
 2014-03-23 14:38:53 +00:00
Jonas Maebe
7ea92f48cc * cleaned up do_spill_replace() 
git-svn-id: trunk@27107 -
 2014-03-11 23:19:01 +00:00
Jonas Maebe
45e03d768e * handle ARM PIC jump tables in determining the maximum offset for 
pc-relative loads

git-svn-id: trunk@27105 -
 2014-03-11 23:18:54 +00:00
florian
6deb0b35b5 * handle fpu_vfpv3_d16 properly for thumb2 
git-svn-id: trunk@27102 -
 2014-03-11 21:25:03 +00:00
Jonas Maebe
4065483a50 * completed thlcgobj.location_force_fpureg(), use it everywhere and removed 
ncgutil/thlcg2ll.location_force_fpureg()

git-svn-id: trunk@27071 -
 2014-03-10 09:01:05 +00:00
Jonas Maebe
e9268a0a14 * synchronised with trunk up till r26975 
git-svn-id: branches/hlcgllvm@26976 -
 2014-03-06 21:36:58 +00:00
Jeppe Johansen
95589fb1e2 Apply DataMov2Data to MLA and MLS too. Those have over 4 operands. 
git-svn-id: trunk@26912 -
 2014-03-01 14:21:04 +00:00
florian
ac85d44899 * do OpCmp2OpS optimization also if after cmp follows an appropriate mov 
git-svn-id: trunk@26801 -
 2014-02-16 18:39:55 +00:00
masta
2d2cab0e7a Fix some internalerror codes in the ARM CG 
git-svn-id: trunk@26701 -
 2014-02-07 12:15:08 +00:00
florian
829764e96b + replace registers to spill in mov instructions and convert them into ldr/str 
git-svn-id: trunk@26677 -
 2014-02-05 18:19:41 +00:00
florian
9e4c130bc4 * do not allocate unnecessarily an extra pair of registers when multiplying int64s on arm 
git-svn-id: trunk@26672 -
 2014-02-04 22:02:51 +00:00
Jeppe Johansen
6861cbcf16 Allow FoldShiftLdrStr for all sizes of LDR/STR, and disable it for references that post/pre increment the base register on Thumb-2 targets. 
git-svn-id: trunk@26671 -
 2014-02-04 17:29:13 +00:00
masta
a72a3f4e01 Little cleanup after r26669, no functional changes 
git-svn-id: trunk@26670 -
 2014-02-04 08:04:08 +00:00
masta
80d2ee8ad0 Don't reuse registers on ARM 64 bits shift 
git-svn-id: trunk@26669 -
 2014-02-03 23:47:28 +00:00
sergei
9c1f917e3a * a_call_ref functionality cannot be implemented efficiently at code generator level, because references need specific preparations at earlier points. Moved this support to tcgcallnode and its x86 descendants, and got rid of all ifdef's around. 
+ x86 targets now directly call procedure variables located in references.
- a_call_ref method removed from tcg and thlcgobj.

git-svn-id: trunk@26666 -
 2014-02-03 13:28:56 +00:00
Jeppe Johansen
07b2982e77 Don't do ARM FoldShiftLdrStr peephole optimization if there's an offset in the reference. 
Use UXTH+UXTB instructions instead of two shifts on processors that supports that.
Eliminate internalerror when constant pointers are typecast as arrays.

git-svn-id: trunk@26647 -
 2014-02-01 13:29:35 +00:00
masta
3f8549365a Don't schedule LDRD on ARM 
The load scheduler does not handle LDRD correctly right now, but it does
not prevent A_LDR with PF_D set from beeing scheduled.

git-svn-id: trunk@26637 -
 2014-01-30 21:53:03 +00:00
Jeppe Johansen
257b1affaa Fixed previous fix of LsrAnd2Lsr optimization. 
Added an extra condition for <ARMv6 processors in MLA/MLS optimization.

git-svn-id: trunk@26620 -
 2014-01-29 22:22:58 +00:00
Jeppe Johansen
f773334374 Fixed LsrAnd2Lsr peephole optimization for ARM. 
git-svn-id: trunk@26619 -
 2014-01-29 21:35:28 +00:00
Jeppe Johansen
3b4f59c316 Fixed MLA/MLS peephole optimization and moved it to the generic ARM peephole optimizer. 
git-svn-id: trunk@26613 -
 2014-01-29 17:28:13 +00:00
Jeppe Johansen
184baa3f99 Fixed invalid peephole optimization of ADD/SUB(SP) instructions for ARMv7*M targets. 
git-svn-id: trunk@26612 -
 2014-01-29 17:12:57 +00:00
masta
9e0af11ad8 Rerun the peephole optimizer after removing the current instruction. 
This lets the optimizer pickup on more possible optimizations.

git-svn-id: trunk@26606 -
 2014-01-28 16:00:51 +00:00
masta
57ff589ec7 Always set p to the next instruction after removing p from asml. 
Some time ago we introduced GetNextInstructionUsingReg, which might
return an instruction a couple of instructions away from our current
location. Most of the code then just returned the new instruction (hp1)
instead of the instruction following p. This could prevent the peephole
optimizer from finding possible optimizations.

git-svn-id: trunk@26605 -
 2014-01-28 16:00:47 +00:00
masta
c644503daf Add MovLdr2Ldr peephole optimizer for ARM 
The existing LdrLdr2LdrMov optimizer will generate a lot of
sequences like this:

ldr regA, [...]
mov regB, regA
ldr regB, [regB, ...]

this now gets changed to

ldr regA, [...]
ldr regB, [regA, ...]

this saves an instruction and might open up more possibilities for the load scheduler.

git-svn-id: trunk@26603 -
 2014-01-28 13:20:35 +00:00
masta
77d12f61a2 Handle LDRD and STRD correctly in RegInInstruction for ARM 
LDRD and STRD only have the first even numbered register in their instruction operands,
this additional code will also check for the register following it.
Example:
  ldrd r0, [r13]

The old code will only detect r0 as in use, not the implicit r1.

git-svn-id: trunk@26602 -
 2014-01-28 13:20:26 +00:00
masta
0736bf4ded Try to change typical constant AND-masking operations into shifts for ARM 
If the constant only contains a string of ones starting from lsb or msb
we can shift out the bits accordingly, opening up some possibilities for
the peephole optimizer to fold at least one shift into another
operation.

git-svn-id: trunk@26565 -
 2014-01-22 20:21:02 +00:00
nickysn
85dd9e5789 + added a size parameter to optimize_op_const and do a sign extension of the 'a' parameter up from the specified size, so that things like (i and $ffffffff) get optimized away the same way as (i and -1) 
git-svn-id: trunk@26561 -
 2014-01-22 15:00:34 +00:00
pierre
b158ad6a9c Handle asmextraopt in arm assembler 
git-svn-id: trunk@26545 -
 2014-01-21 00:21:34 +00:00
sergei
a3efd9e1df + Added method taddnode.use_generic_mul64bit, allowing it to inline full 64-bit multiplications, and fixed ARM to comply (it was not checking for possible 32x32 to 64 optimization after detecting a 64-bit operand, so recently added code for 32x32 to 64 bit optimization was inactive). 
git-svn-id: trunk@26500 -
 2014-01-18 09:59:59 +00:00
Jeppe Johansen
123742647c Fixed problem in estimation of stack size for thumb targets. Types passed by value were not handled properly. 
git-svn-id: trunk@26458 -
 2014-01-14 19:27:15 +00:00
masta
fb52392e20 Reformat and comment is_thumb32_imm 
I've just regrouped the conditions a bit for easier understanding. No
functional changes.

git-svn-id: trunk@26449 -
 2014-01-13 21:32:28 +00:00
masta
3ab665e554 Try to split constant XORs into two shiftimms on ARM. 
git-svn-id: trunk@26448 -
 2014-01-13 21:32:24 +00:00
florian
1fc6316cbc * use generic 32*32 -> 64 bit multiplication on arm thumb 
git-svn-id: trunk@26359 -
 2014-01-02 15:23:12 +00:00
masta
bcec29f1b4 Disable generation of UMULL when generating thumb1 code 
git-svn-id: trunk@26355 -
 2014-01-02 13:22:15 +00:00
masta
e5b3d89a5d Add CPUARM_HAS_UMULL flag 
Pre armv4 and all *M variants to not support UMULL and SMULL.

The Flag now gets used for 32x32->64 and 64x64->64 optimized code.

git-svn-id: trunk@26354 -
 2014-01-02 13:06:18 +00:00
masta
f8889e3d6d Use optimize_op_const in ARM cg 
This uses the generic optimizations done in optimize_op_const. Due to
this we can also drop some of the optimizations done in the arm-specific
code.

git-svn-id: trunk@26348 -
 2014-01-01 18:26:42 +00:00
masta
d32abdf047 Little cleanup in tarmaddnode.second_add64bit 
git-svn-id: trunk@26347 -
 2014-01-01 18:26:38 +00:00
masta
cec633e86e Optimized support for 32x32 => 64bit multiplications on ARM 
This code uses UMULL and SMULL to perform the multiplications, which
take two 32bit source registers and two 32bit destination registers.

git-svn-id: trunk@26346 -
 2014-01-01 18:26:29 +00:00
florian
de3a116a28 * handle records with size 0 as function results correctly 
git-svn-id: trunk@26303 -
 2013-12-28 20:19:56 +00:00
florian
561ec1f782 * unified internal errors 
git-svn-id: trunk@26302 -
 2013-12-28 20:19:54 +00:00
Jeppe Johansen
d24cbbf9f5 Changed debug information to dwarf for ARM_embedded, and set local minimum alignment to 4. 
Fixed a bug where ARMv7M targets would not use the DIV instructions.
Moved many size-optimizing Thumb2 peephole optimizations to PostPeepHoleOptsCpu. Previously those optimizations could make it impossible to reuse the shared arm peephole optimizations.
Reenabled a fixed MLA/MLS peephole optimization.
Refactored some FindRegDealloc+regLoadedWithNewValue into RegEndOfLife calls.
Fixed some broken UXTB/UXTH optimizations. Previously they would also match UXT* instructions with ROR shifter ops.

git-svn-id: trunk@26198 -
 2013-12-08 16:50:15 +00:00
Károly Balogh
71e492db1b made arm-linux system unit compilable on anything but Thumb2 after r26161 
git-svn-id: trunk@26175 -
 2013-12-03 16:36:34 +00:00
florian
4d5119bf1c * fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables 
git-svn-id: trunk@26161 -
 2013-12-01 17:02:08 +00:00
sergei
97a706c672 + Add definitions for ELF header flags. 
git-svn-id: trunk@26137 -
 2013-11-25 13:59:12 +00:00
Jonas Maebe
b6d279d4aa * don't transform div-by-power-of-2 into a shift when overflow checking is 
enabled (mantis #23849)

git-svn-id: trunk@26089 -
 2013-11-14 15:47:49 +00:00
Jonas Maebe
25fab5b0b6 + support for array vecnodes on the llvm target, both for regular and for 
bitpacked arrays:
   o separate the element size from the index when constructing the memory
     references, so we can easily use the llvm getelementptr instruction
   o handle conversion of s80real values from their array declaration
     as array elements to floating point values when loading them

git-svn-id: branches/hlcgllvm@26050 -
 2013-11-11 11:16:09 +00:00
Jonas Maebe
5ef93e85b8 + added extra "orgsupreg" parameter to do_spill_read/do_spill_written/ 
do_spill_replace routines, will be necessary by llvm register
    allocator to determine the tdef corresponding to that register
  * replaced uses of taicpu with tai_cpu_abstract_sym in the register
    allocator so that it can work both with taicpu and taillvm instructions

git-svn-id: branches/hlcgllvm@26043 -
 2013-11-11 11:15:43 +00:00
Jonas Maebe
99de108c68 * renamed all paramanagers to tcpuparamanager so the llvm paramanager can 
derive from them without ifdefs

git-svn-id: branches/hlcgllvm@26039 -
 2013-11-11 11:15:27 +00:00
florian
24d88edf37 * fixes arm building after 26004 
git-svn-id: trunk@26012 -
 2013-11-10 17:46:03 +00:00
Károly Balogh
628149d923 support label offsets for ARM like GAS, allows things like ADR r4, .label + 256 
git-svn-id: trunk@25938 -
 2013-11-05 18:10:54 +00:00
Károly Balogh
b67e4fb8b3 added the ADR ARM pseudo instruction to instruction list 
git-svn-id: trunk@25936 -
 2013-11-05 13:16:33 +00:00
Jonas Maebe
555634b755 * (re)set upper bits of register when appropriate for all operations in 
a_op_reg_reg() (except for NOT, which was already handled correctly)
    + test

git-svn-id: trunk@25840 -
 2013-10-22 07:41:52 +00:00
Jonas Maebe
10ae87f11c * fixed LdrLdr2LdrMov optimisation in case the first and second ldr have 
a different size (disable it in that case) + test

git-svn-id: trunk@25778 -
 2013-10-14 12:49:34 +00:00
Jonas Maebe
5276159e77 * correct ofset for saving floating point registers + explanation behind 
the calculation (fixes make cycle on ARMHF)

git-svn-id: trunk@25777 -
 2013-10-14 12:49:31 +00:00
Jonas Maebe
31a3122b91 * fixed LsrAnd2Lsr test by replacing the existing buggy check with comparing 
the outcome of the original and the optimised sequence and seeing whether
    it's same + test

git-svn-id: trunk@25776 -
 2013-10-14 12:49:28 +00:00
sergei
a5ae26da7e * Moved SkipEntryExitMarker method from ARM optimizer to the base one, since it is not target-dependent. Now it can be reused by other targets. 
git-svn-id: trunk@25738 -
 2013-10-10 21:12:49 +00:00
svenbarth
c48d572996 Implement support for saving and restoring address registers. 
cgobj.pas, tcg:
  * g_save_registers: add the amount of used address registers to size as well
  * g_save_registers: save all used address registers
  * g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
  * rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
  * add a saved_address_registers variable with one entry of RS_INVALID

At least a "make fullcycle" did complete.

git-svn-id: trunk@25664 -
 2013-10-05 21:43:42 +00:00
florian
73e6af4864 + cpu flag CPUARM_HAS_THUMB_IDIV 
* test for CPUARM_HAS_THUMB_IDIV instead the CPU type when creating sdiv/udiv code

git-svn-id: trunk@25648 -
 2013-10-05 12:38:55 +00:00
florian
8fb7cf822b * unified internal errors 
git-svn-id: trunk@25647 -
 2013-10-05 12:37:46 +00:00
florian
e0f48b9f02 * calculate stack correction on exit correctly if stack parameters are passed 
git-svn-id: trunk@25427 -
 2013-09-05 21:40:33 +00:00
florian
36e6f99843 * fix tthumbcgarm.g_flags2reg, mov reg,#imm for thumb updates the flags 
git-svn-id: trunk@25426 -
 2013-09-05 21:40:30 +00:00
florian
e2ec3bbcb0 * do shifts for sign/zero extensions correctly 
git-svn-id: trunk@25418 -
 2013-09-04 21:00:46 +00:00
Károly Balogh
2c49af3191 added missing closing parentheses 
git-svn-id: trunk@25413 -
 2013-09-04 14:56:53 +00:00
florian
333e84202f * fixed a_load_reg_reg for thumb 
git-svn-id: trunk@25408 -
 2013-09-03 21:11:02 +00:00
florian
7ef37b5d2a * PLD is not supported by thumb 
git-svn-id: trunk@25407 -
 2013-09-03 21:09:41 +00:00
florian
cb1f38b0af * strd/ldrd are not supported by thumb 
git-svn-id: trunk@25406 -
 2013-09-03 21:09:13 +00:00
Károly Balogh
86cb4d0c12 use a TSuperRegister instead of an aint 
git-svn-id: trunk@25383 -
 2013-08-28 12:58:29 +00:00
Károly Balogh
c677f1fd69 trying harder to follow the code style (no functional changes) 
git-svn-id: trunk@25382 -
 2013-08-28 11:25:15 +00:00
Károly Balogh
25619d4991 removed the const-in-the-left internalerror 
git-svn-id: trunk@25380 -
 2013-08-27 16:18:53 +00:00
Károly Balogh
cb4d01627f save an extra reg if it's required to keep 64bit stack alignment on ARM 
git-svn-id: trunk@25379 -
 2013-08-27 12:49:50 +00:00
masta
ff95d42216 Fix ShiftShift2Shift 1 ARM-peephole optimizer 
The previous code deleted the newly inserted instruction instead of the
existing one, which obviously broke code.

Assembly:
  mov r0, r0, lsr #23
  mov r0, r0, lsr #23

transformed into:
  mov r0, r0, lsr #23

expected was:
  mov r0, #0

The problem only shows up in the very unlikely case of two LSR/ASR or
two LSL following on each other and having a total shift of more than 31
bits.

This fixes test/opt/tarmshift.pp

I've also removed the {%norun} directive from tarmshift.pp as this test
does only make sense when it also runs.

git-svn-id: trunk@25374 -
 2013-08-26 17:41:54 +00:00
florian
d4968e054b + arm: tsettings.instructionset 
* the selected instruction set is now independent from the cpu type: e.g. armv7-a can perfectly execute thumb(2) code

git-svn-id: trunk@25370 -
 2013-08-25 21:56:12 +00:00
florian
7cef301e84 * disable optimization LdrbAnd2Ldrb for arm thumb as it is currently done 
git-svn-id: trunk@25356 -
 2013-08-23 18:41:26 +00:00
florian
f34bee1df7 * arm thumb does not support ror reg1,reg2,#imm 
git-svn-id: trunk@25355 -
 2013-08-23 18:41:24 +00:00
florian
950194678a * handle jump tables correctly when inserting constant pools on arm thumb 
git-svn-id: trunk@25354 -
 2013-08-23 18:41:21 +00:00
Károly Balogh
6591a24bd3 removed some code which must never be called, added an internalerror() instead 
git-svn-id: trunk@25352 -
 2013-08-23 15:58:37 +00:00
florian
e514e84c83 * first_moddivint should not change the return type if div/mul/add is used 
* use create_internal when creating internally add nodes

git-svn-id: trunk@25351 -
 2013-08-23 15:23:00 +00:00
florian
3ebe708574 * do not use r13/r15 for certain data processing operations 
* correct OP_AND with certain types of constants

git-svn-id: trunk@25350 -
 2013-08-23 15:22:58 +00:00
florian
2fe48077b2 * using r13 and r15 is on arm thumb2 also forbidden under certain conditions for the instructions A_SUB,A_AND,A_BIC,A_EOR 
git-svn-id: trunk@25349 -
 2013-08-23 15:22:55 +00:00
florian
d5ddf39f73 * do not do the RedundantMovProcess optimization when the involved registers are r13 or r15 and if the target is arm thumb(2) 
git-svn-id: trunk@25348 -
 2013-08-23 15:22:53 +00:00
florian
b4c7b40049 * do not split statements following A_IT* instructions on arm thumb2 when inserting constant pools 
git-svn-id: trunk@25347 -
 2013-08-23 15:22:51 +00:00
florian
8884f1c0bf * arm thumb2 supports only left shifted index registers up to 3 bits 
git-svn-id: trunk@25346 -
 2013-08-23 15:22:49 +00:00
florian
6df2917d93 * fix spilling of vfp instructions 
* spelling mistake fixed

git-svn-id: trunk@25345 -
 2013-08-23 15:22:46 +00:00
florian
c350c3a5e4 * arm thumb2 does not understand tst reg1,reg2,lsl reg3 
git-svn-id: trunk@25344 -
 2013-08-23 15:22:44 +00:00
florian
bb73a2891b * prevent generation of mul/mla statements with illegal registers 
git-svn-id: trunk@25343 -
 2013-08-23 15:22:41 +00:00
Jonas Maebe
4ec9ec2009 + PIC support for Darwin/ARM: 
o does not use GOT
   o enabled by default like for other Darwin platforms
  - removed Darwin/ARM call stub support: no longer needed with current
    Xcode versions (at least Xcode 4.2+), and we didn't support PIC
    in them yet

git-svn-id: trunk@25325 -
 2013-08-22 08:14:24 +00:00
Jonas Maebe
8ffb704b8c * don't split address labels from the instruction they belong with when 
rescheduling (needed for GOT-less PIC)

git-svn-id: trunk@25324 -
 2013-08-22 08:14:18 +00:00
Jonas Maebe
b31e5c2536 + PIC support for ARM jump tables (only for plain ARM right now, not 
yet for thumb/thumb2)

git-svn-id: trunk@25323 -
 2013-08-21 22:28:24 +00:00
florian
6606955b88 + basic support for pic on arm-linux 
git-svn-id: trunk@25297 -
 2013-08-19 21:35:37 +00:00
florian
2806947a8f + FindRegAllocBackward 
* search reg. allocations backward in RemoveSuperfluousMove because the changed instruction could be the first one in a list

git-svn-id: trunk@25289 -
 2013-08-18 18:56:56 +00:00
Jonas Maebe
57cdd8c106 * set symbol type/binding of data referred by ppc and arm/darwin stubs (part 
of r25264, fixes internalerror 2013081601 after r25266)

git-svn-id: trunk@25275 -
 2013-08-17 16:26:37 +00:00
Jonas Maebe
3b9b6a0cd7 * explicitly define the asmsymbols for Darwin call stubs as local 
git-svn-id: trunk@25264 -
 2013-08-16 10:07:46 +00:00
Károly Balogh
614afca755 ARM: try to inline 64bit multiplication for the most common cases instead of calling FPC_MUL_ helpers (results in 5-10x speedup) 
git-svn-id: trunk@25189 -
 2013-07-30 14:40:50 +00:00
florian
6f5bcaae2b * UMUL et al. have only register restrictions on arm below v6 
git-svn-id: trunk@25171 -
 2013-07-24 20:18:12 +00:00
Jeppe Johansen
d89b9a4311 Add support in ARM assembler reader for ldr reg, =literal syntax 
git-svn-id: trunk@25157 -
 2013-07-21 16:06:57 +00:00
Jeppe Johansen
fdcc68cfd7 Disabled preindex/postindexed peephole optimizations for Thumb and Thumb2 
git-svn-id: trunk@25156 -
 2013-07-21 14:21:16 +00:00
Jeppe Johansen
f3273fa87d Optimize Add/Sub+Ldr/Str by using preindexed references 
git-svn-id: trunk@24789 -
 2013-06-02 21:51:12 +00:00
Jeppe Johansen
2d823452b7 The scheduler pass of the ARM optimizer left markers in the instruction list, which could prevent further peephole optimizations 
git-svn-id: trunk@24781 -
 2013-06-02 16:37:41 +00:00
Jeppe Johansen
570b40faed Signed modulus by 2 on ARM with no division is optimized to a series of instructions instead of calling fpc_mod_longint. 
An ASR is removed from signed division by 2.

git-svn-id: trunk@24778 -
 2013-06-02 14:44:06 +00:00
Jonas Maebe
9938169d2c * don't use the paracgsize in get_paraloc_def(), because it generally 
contains the tcgsize of the entire parameter rather than only of
    what is left (-> calculate it from the remaining parameter length)

git-svn-id: trunk@24776 -
 2013-06-02 14:05:07 +00:00
Jonas Maebe
7566ddcc8f * add a tdef to each parameter location and set it for all target 
backends (not yet used, will be used in high level code generator)

git-svn-id: trunk@24761 -
 2013-06-02 10:24:02 +00:00
florian
4056194e7c * don't ignore by accident the next instruction after a newly inserted constant pool 
git-svn-id: trunk@24677 -
 2013-05-31 21:29:08 +00:00
florian
3a393f839e * do not reuse register locations on arm fpa/vfp 
git-svn-id: trunk@24676 -
 2013-05-31 21:29:05 +00:00
masta
8c32802fcf Added LdrbAnd2Ldrb Peephole optimizer for arm 
Changes the following code:
  ldrb dst1, [REF]
  and  dst2, dst1, #255
  # dealloc dst1
to
  ldrb dst2, [REF]

git-svn-id: trunk@24672 -
 2013-05-31 17:36:54 +00:00
Jonas Maebe
5051453806 + support for LOC_(C)MMREGISTER in hlcg 
o migrated location_force_mmregister_scalar from ncgutil to hlcgobj

git-svn-id: trunk@24661 -
 2013-05-31 12:05:14 +00:00
masta
073cab8d86 Optimize FoldShiftLdrStr in ARM Peephole optimizer 
The optimizer now juggles around the base and index register if that opens
up the possibility of folding the shift into the instruction.

This can only be done in the case of addressmode=AM_OFFSET, in case of
[AM_POSTINDEXED, AM_PREINDEXED] we can not move the base register, as this
would cause havoc and destruction.

git-svn-id: trunk@24645 -
 2013-05-30 16:13:58 +00:00
Jeppe Johansen
0bb8d24e24 Add some immediate forms of shift instructions to tcgthumb.a_op_const_reg 
git-svn-id: trunk@24637 -
 2013-05-30 12:07:32 +00:00
Jeppe Johansen
e5066a5f43 Update jumptabel generation for ARM Thumb 
git-svn-id: trunk@24636 -
 2013-05-30 12:06:30 +00:00
Jeppe Johansen
c4263ced51 Disable one peephole optimization for Thumb 
git-svn-id: trunk@24635 -
 2013-05-30 12:05:27 +00:00
florian
e6489ed7d2 * arm thumb: do not generate illegal ror instructions 
git-svn-id: trunk@24439 -
 2013-05-04 22:00:17 +00:00
florian
ccdd4437d6 * arm thumb: do not cause bxx getting too long ranges when inserting constant blocks 
git-svn-id: trunk@24437 -
 2013-05-04 20:36:08 +00:00
florian
7bea00e5fb * arm thumb: allow interface trampolines to non-virtual methods with large offsets 
git-svn-id: trunk@24434 -
 2013-05-04 19:54:03 +00:00
florian
ed2825fbb0 * arm thumb: handle constants in second_cmpsmallset correctly 
git-svn-id: trunk@24432 -
 2013-05-04 19:38:12 +00:00
florian
1de40c8de7 * arm thumb: fix spilling with offsets >1020 
git-svn-id: trunk@24419 -
 2013-05-04 10:51:01 +00:00
florian
6197330bad * arm thumb: take care of constant restrictions when creating interface wrappers for non-virtual methods 
git-svn-id: trunk@24415 -
 2013-05-03 21:12:16 +00:00
florian
f3b7f6197b * arm thumb: generate proper code for rol 
git-svn-id: trunk@24414 -
 2013-05-03 20:53:58 +00:00
florian
cec28ef512 * when inserting pc relative data blocks on arm thumb, avoid negative pc offsets, if needed, the data is copied 
a short test with the rtl shows that this happens exactly once in the rtl, so it is feasible to do so

git-svn-id: trunk@24413 -
 2013-05-03 20:45:26 +00:00
florian
0e9b8adb7a patch by Michael Ring: 
+ support of several armv6m MCUs for arm-embedded
* renamed lpc1343 unit to lpc13xx
+ more lpc13xx MCUs added

git-svn-id: trunk@24379 -
 2013-04-29 19:57:08 +00:00
florian
ec69ed5b3c * spelling fixed 
git-svn-id: trunk@24205 -
 2013-04-08 11:50:09 +00:00
florian
f80b6f4774 * arm thumb: take care of large offsets in interface wrappers 
git-svn-id: trunk@24203 -
 2013-04-07 21:56:37 +00:00
florian
dee35abf41 * arm thumb: let all registers used in a ldr/str operation interfere with the "hi" registers 
git-svn-id: trunk@24202 -
 2013-04-07 21:39:30 +00:00
florian
36a32e153d + arm thumb: tarmloadparentfpnode moves the stack pointer to a different register to avoid illegal instruction encodings 
git-svn-id: trunk@24201 -
 2013-04-07 21:29:12 +00:00
florian
e41b7b1b94 * arm thumb: strh/ldrh does not allow stack pointer based references with offset 
git-svn-id: trunk@24200 -
 2013-04-07 21:27:59 +00:00
florian
7ba197a221 * fix stack parameter handling for arm thumb 
* fix entry/exit code generation for arm thumb

git-svn-id: trunk@24197 -
 2013-04-07 21:01:15 +00:00
florian
f9ef8e90da + a_op_const_reg_reg for arm thumb taking care of availability of add sp,sp, ... 
* handle references with base and index on arm thumb correctly

git-svn-id: trunk@24196 -
 2013-04-07 21:01:11 +00:00
florian
9bbc24b5e3 * r13 might be used only under certain circumstance in memory reference on arm thumb 
git-svn-id: trunk@24195 -
 2013-04-07 21:01:08 +00:00
florian
79334242a2 * arm thumb uses always the stack pointer as frame pointer 
git-svn-id: trunk@24194 -
 2013-04-07 21:01:05 +00:00
florian
f25a905904 * fix register allocation initalization for arm thumb 
* avoid that the register allocator creates code which writes to frame/stack pointer

git-svn-id: trunk@24190 -
 2013-04-07 21:00:50 +00:00