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1161 Commits

Author SHA1 Message Date
Jonas Maebe
1131b08d6d * changed idtext of as_darwin to AS-DARWIN, so it can be explicitly 
selected via -Aas-darwin (since it compares uppercased strings)

git-svn-id: trunk@31808 -
 2015-09-24 06:49:29 +00:00
Jonas Maebe
8155d759dc - reverted r31806, it breaks building on non-Darwin (mantis #28716) 
git-svn-id: trunk@31807 -
 2015-09-24 06:44:12 +00:00
Jonas Maebe
c0b451e788 - removed as_darwin, since there is no difference with as_gas (there is no 
GNU as from binutils for Darwin, and Apple's "as" is based on an old
    version of GNU as)
   o this will not cause any backward compatibility problems, as the
     previous identifier for as_darwin was "AS-Darwin" and the compiler
     compared the uppercase value of the -A parameter to the identifier,
     so it was not explicitly selectable earlier. The new name is "AS",
     so it is explicitly selectable via -Aas like on other platforms.

git-svn-id: trunk@31806 -
 2015-09-23 21:25:38 +00:00
Jonas Maebe
840c043c75 * always use unified assembler syntax on Darwin (required by Xcode 7+) 
git-svn-id: trunk@31805 -
 2015-09-23 20:38:18 +00:00
Jonas Maebe
c5f64a51da * also support unified syntax for non-thumb2 (not yet activatable/usable) 
git-svn-id: trunk@31804 -
 2015-09-23 20:38:14 +00:00
yury
61a1976e09 * Removed a leftover of my code. It is not needed anymore. 
git-svn-id: trunk@31755 -
 2015-09-18 10:34:27 +00:00
yury
432248cbf1 * Removed lot of unused vars. 
git-svn-id: trunk@31732 -
 2015-09-17 12:48:58 +00:00
yury
40628fa614 * Removed unused vars. 
git-svn-id: trunk@31731 -
 2015-09-17 12:24:59 +00:00
yury
80e5eb0c5d * ARM: I hope this is a final proper fix for GOT initialization. + Test. 
git-svn-id: trunk@31730 -
 2015-09-17 12:18:04 +00:00
yury
1dff9bf025 * ARM: Fixed GOT init when optimization is off. 
git-svn-id: trunk@31728 -
 2015-09-16 21:30:20 +00:00
yury
f2c8824963 * ARM: Do not use R9 as a fixed GOT register. 
git-svn-id: trunk@31712 -
 2015-09-16 13:52:15 +00:00
yury
df9d6db398 * Fixed instruction re-scheduler for ARM in case of PIC. 
git-svn-id: trunk@31706 -
 2015-09-16 11:54:12 +00:00
yury
61c0448903 * Big fix for ARM GOT support to make it work: 
- Fixed access to symbols with offset.
  - Always use register R9 for GOT pointer to prevent bugs when free register limit is reached in a function.
  - GOT is not needed for function calls by name.

git-svn-id: trunk@31681 -
 2015-09-14 23:15:10 +00:00
Jonas Maebe
991e1f49bd * store a pointer to the used tasminfo record in every assembler writer, so 
that we can use assembler writers with different conventions from the
    currently set target_asm (e.g. an x86 assembler writer for inline assembly
    in LLVM IR)

git-svn-id: trunk@31628 -
 2015-09-12 23:32:13 +00:00
Jonas Maebe
b3d0197f98 * factored out the output file handling (mostly writing data) from the 
external assembler writer, so we can reuse the archtecture-specific
    writers to write inline assembly in LLVM IR files

git-svn-id: trunk@31625 -
 2015-09-12 23:32:01 +00:00
Jeppe Johansen
3cb9be73bc Moved tcontrollerdatatype out into cpuinfo. 
Added cputype and fputype info to tcontrollerdatatype arrays.

git-svn-id: trunk@31574 -
 2015-09-07 20:36:54 +00:00
florian
4d349c9c71 * take care of limited offsets of stf/ldf, resolves issue #23620 
git-svn-id: trunk@31572 -
 2015-09-07 20:14:27 +00:00
Jeppe Johansen
297c17d4f0 Add missing prefix for VCMP for FPv4_S16. 
git-svn-id: trunk@31562 -
 2015-09-06 20:34:08 +00:00
Jeppe Johansen
dac294c680 Fix ARMv3/ARMv2A support. 
git-svn-id: trunk@31561 -
 2015-09-06 20:33:26 +00:00
Jonas Maebe
f374b81c12 * disabled ARM-specific code for smallset in-operations on big endian targets, 
as it's also little endian-specific (mantis #28592)

git-svn-id: trunk@31466 -
 2015-08-31 13:06:42 +00:00
Jonas Maebe
0fc1fd6ac1 * replaced current_procinfo.currtrue/falselabel with storing the true/false 
labels of LOC_JUMP in the node's location. This generates some extra jumps
    for short circuit boolean and/or-expressions if optimizations are off, but
    with optimisations enabled the generated code is the same (except for JVM
    because the jump threading optimisation isn't enabled there yet).

git-svn-id: trunk@31431 -
 2015-08-27 18:28:57 +00:00
Jonas Maebe
10b2ea3b1b * use handle_locjump() instead of local inlined version 
git-svn-id: trunk@31430 -
 2015-08-27 18:28:52 +00:00
Jeppe Johansen
2b80d46492 Added STM32F7xx controller units and types. 
git-svn-id: trunk@31257 -
 2015-07-31 22:21:16 +00:00
Jonas Maebe
f40ea04540 * changed getarraydef() into a tarraydef.getreusable() class method 
git-svn-id: trunk@31147 -
 2015-06-23 21:23:18 +00:00
Jonas Maebe
f402b0d7df * changed getpointerdef() into a tpointerdef.getreusable() class method 
o allows removing the ugly x86 hacks

git-svn-id: trunk@31144 -
 2015-06-22 08:17:49 +00:00
Jeppe Johansen
36dfe750d8 Added Freescale MK20D7 controller support. 
git-svn-id: trunk@30925 -
 2015-05-28 11:46:22 +00:00
florian
b4fc11fe06 * implemented r30870 for all platforms: pass dyn. array parameters like pointer parameters so typically in a register 
git-svn-id: trunk@30878 -
 2015-05-17 12:29:28 +00:00
Jeppe Johansen
6662cb6dd5 ARMv6M was missing alignments for jumptables 
git-svn-id: trunk@30775 -
 2015-05-03 16:16:32 +00:00
florian
b222d0b663 * correctly handle LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF in second_int_to_bool, resolves issue #28007 
git-svn-id: trunk@30765 -
 2015-05-02 13:52:50 +00:00
florian
7dd1d6aa77 o fixes handling of iso i/o parameters/program parameters: 
* explicit reset is needed
  * variable must be declared again

git-svn-id: trunk@30757 -
 2015-05-01 20:58:31 +00:00
Jeppe Johansen
b6729a8f0b Workaround for IE 20060521 when building the ARM compiler 
git-svn-id: trunk@30733 -
 2015-04-26 20:10:57 +00:00
Jeppe Johansen
65a69129c5 Add initial support for STM32F429 core 
git-svn-id: trunk@30599 -
 2015-04-14 21:55:37 +00:00
Jeppe Johansen
f31f87e8c7 Fix spilling_get_operation_type for MRS and MSR instructions 
git-svn-id: trunk@30590 -
 2015-04-14 17:20:47 +00:00
Jonas Maebe
9079227c56 * don't give an internalerror when trying to prefetch a regvar or even 
something without a location at all; it's a hint/optional operation,
    so if there's nothing to prefetch just don't do anything
    (mantis #27811)

git-svn-id: trunk@30502 -
 2015-04-08 20:35:13 +00:00
Jonas Maebe
61e4a1b811 + added tasmlist parameter to getintparaloc() (needed for llvm) 
git-svn-id: trunk@30429 -
 2015-04-04 14:29:16 +00:00
Jonas Maebe
201121d7c9 * synchronised with trunk till r30345 
git-svn-id: branches/hlcgllvm@30349 -
 2015-03-28 12:28:15 +00:00
Jonas Maebe
687bb15299 * renamed getdatalabel() to getglobaldatalabel 
git-svn-id: branches/hlcgllvm@30336 -
 2015-03-27 21:25:34 +00:00
Jeppe Johansen
fa5bd1c513 ARMv7M supports UMULL. 
Fix missing conflicts for multiplication instructions for >=ARMv6.

git-svn-id: trunk@30276 -
 2015-03-22 14:39:43 +00:00
Jeppe Johansen
5ca1740bee Fix issue in is_thumb32_imm. imm<11:10> have to be non-zero meaning the rotate only works from 8 to 31. Caused 0x8000001F to be mistaken for a valid immediate. 
git-svn-id: trunk@30266 -
 2015-03-21 12:46:45 +00:00
Jeppe Johansen
09acd9b1ab Add workaround for ARM thumb when using GAS. 
git-svn-id: trunk@30254 -
 2015-03-17 21:24:07 +00:00
Jonas Maebe
bd203a5b57 * synchronised with trunk till r30240 
git-svn-id: branches/hlcgllvm@30241 -
 2015-03-15 19:44:58 +00:00
Jeppe Johansen
f92f0751f4 Fix selection of LDR/STR instructions in thumb mode. Most forms don't support pre or post indexing. 
Fix emission of offsets.

git-svn-id: trunk@30234 -
 2015-03-15 12:12:13 +00:00
Jonas Maebe
8445381929 * merged ait_set and ait_thumb_set into a single tai class 
(tai_symbolpair)

git-svn-id: trunk@30197 -
 2015-03-14 18:35:28 +00:00
Jeppe Johansen
52e505bff7 Fixed internal error in GOT related code for ARM internal assembler. 
git-svn-id: trunk@30188 -
 2015-03-14 16:03:16 +00:00
Jeppe Johansen
439027a8de Add most pre-UAL VFP instruction forms. 
Add fused mac instructions for VFPv4.

git-svn-id: trunk@30187 -
 2015-03-14 14:59:13 +00:00
Jeppe Johansen
64f127141f Add VFPv4 FPU type for ARM. 
Fix assembler reader so it can read instructions longer than 5 characters.

git-svn-id: trunk@30186 -
 2015-03-14 12:49:07 +00:00
Jeppe Johansen
73abf5e630 Merge from armiw branch. 
Update ARM internal assembler to support most ARM, Thumb and Thumb-2 instructions.
Changed generation of VFP instructions to use UAL mnemonics.
Added divided and unified assembler syntax support to ARM assembly reader.

git-svn-id: trunk@30181 -
 2015-03-13 19:22:27 +00:00
Jeppe Johansen
3d7dce81fe Make MRS and MSR use the right encoding on Thumb architectures. 
Set regnumber_count_bsstart to 128 to be able to search all registers.

git-svn-id: branches/laksen/armiw@30150 -
 2015-03-08 17:30:38 +00:00
Jeppe Johansen
03b9e5117f Fix off by 1 error in assembler reader which prevented B instructions from being parsed. 
git-svn-id: branches/laksen/armiw@30147 -
 2015-03-08 12:52:43 +00:00
Jeppe Johansen
914e9e7b49 Merged from trunk 
git-svn-id: branches/laksen/armiw@30146 -
 2015-03-08 12:33:46 +00:00
Jeppe Johansen
d12b913e70 Add initial support in ARM-embedded for Allwinner A20. 
git-svn-id: trunk@30144 -
 2015-03-08 12:22:57 +00:00
Jonas Maebe
67b8aceaee * synchronized with privatetrunk till r30095 
git-svn-id: branches/hlcgllvm@30101 -
 2015-03-05 20:32:15 +00:00
Jonas Maebe
b2427d04ed * ensure that data pools are not inserted right after add/tbb/tbh-based 
jumptable dispatches

git-svn-id: trunk@30027 -
 2015-02-27 20:52:12 +00:00
Jonas Maebe
2ab7f5c35d * moved x86-specific requirements from the generic bsr/bsf code to the 
x86 code generator (register size constraints)

git-svn-id: trunk@29984 -
 2015-02-23 22:57:18 +00:00
Jonas Maebe
d6de2c03cb * generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe 
o in particular, add tdef size information to the update_reference*()
     methods, and factored out offset adjustments into its own method
   o also make sure the passed size to update_reference*() corresponds to the
     actual size of the index, as it's no longer guaranteed to be ptruint
     since the previous commit

git-svn-id: trunk@29967 -
 2015-02-23 22:56:00 +00:00
Jonas Maebe
3fe0bd065e * ARM assembler reader: don't check for postfixes beyond the length 
of the opcode

git-svn-id: trunk@29823 -
 2015-02-23 22:47:56 +00:00
florian
9eab90d8c4 * always pass the architecture to the arm assembler 
* encode pld/ldrd in arm.inc using .long, so it causes no errors with older architectures settings of the assembler

git-svn-id: trunk@29780 -
 2015-02-21 21:58:30 +00:00
florian
80cc09e350 o fix wince compilation: 
* apparently, wince (or GNU AS for it) does not support blx imm
  * set FPC_IN_SYSTEM directive, so assembler code in divide.inc is compiled right

git-svn-id: trunk@29779 -
 2015-02-21 21:55:56 +00:00
Jeppe Johansen
47dbec3111 Rebase to trunk revision 
git-svn-id: branches/laksen/armiw@29708 -
 2015-02-15 16:08:18 +00:00
Jeppe Johansen
60b3ea8038 Use proper syntax when emitting UAL VFP instructions for all postfix types. 
Fixed postfix of VSQRT instruction.

git-svn-id: branches/laksen/armiw@29591 -
 2015-02-01 09:38:45 +00:00
sergei
9cc0bdd6b9 + Missing part of internal ARM assembler, Mantis #26588. I'm not setting it as default for arm-wince yet, because testing reveals several points in generic code that need adjustments. 
git-svn-id: trunk@29588 -
 2015-01-30 22:45:05 +00:00
sergei
472310d83f * ARM: Fixed interface wrapper generation after r28542 for targets without BX instruction. 
git-svn-id: trunk@29580 -
 2015-01-30 15:00:28 +00:00
Jeppe Johansen
db401f0371 Add missing size postfix to VNEG VFP instruction. 
git-svn-id: branches/laksen/armiw@29436 -
 2015-01-11 13:40:35 +00:00
Jeppe Johansen
2ac11e4b82 Use proper relocation type for Thumb-2 BLX. 
Initialize MM register allocator properly for Thumb-2 cg.

git-svn-id: branches/laksen/armiw@29435 -
 2015-01-11 13:30:52 +00:00
Jeppe Johansen
572076fc4d Add MSR/MRS for ARMv6M/7M. 
Fix bug in FPA LFM/SFM.
Add usermode handling of LDM/STM.

git-svn-id: branches/laksen/armiw@29371 -
 2015-01-02 13:24:03 +00:00
Jeppe Johansen
7390acc426 Merged from recent trunk. 
git-svn-id: branches/laksen/armiw@29369 -
 2015-01-01 23:54:40 +00:00
Jeppe Johansen
f963ff1b5b Add CPSxx instructions, and some missing FPA instructions. 
git-svn-id: branches/laksen/armiw@29368 -
 2015-01-01 21:17:21 +00:00
Jeppe Johansen
ff7af306df Add FPA support. 
git-svn-id: branches/laksen/armiw@29366 -
 2015-01-01 11:18:04 +00:00
Jeppe Johansen
49346b3041 Fix SWI as a pseudo instruction. 
Add VFPv2/3 instruction entries for Thumb2.

git-svn-id: branches/laksen/armiw@29356 -
 2014-12-29 11:34:34 +00:00
Jeppe Johansen
cbd75428c0 Fix an issue with local BLX branches not being turned into BL branches. 
git-svn-id: branches/laksen/armiw@29355 -
 2014-12-28 23:27:30 +00:00
Jeppe Johansen
9a482d5281 Refactor and secure some immediate operand encodings. 
Add some system mode entries, udiv/sdiv in arm mode, and fix bugs in ldrh/strh.

git-svn-id: branches/laksen/armiw@29353 -
 2014-12-28 21:41:06 +00:00
Jeppe Johansen
e7575d9f96 Fix some encoding bugs in ARM modes. Mostly shifts and signindex errors. 
Add FPU mask checking for instructions too.

git-svn-id: branches/laksen/armiw@29352 -
 2014-12-28 16:16:54 +00:00
Jeppe Johansen
97fdfc942b Fix encoding of shifterops for ARM dataprocessing instructions. 
git-svn-id: branches/laksen/armiw@29348 -
 2014-12-28 00:13:06 +00:00
Jeppe Johansen
c284d8f6ba Fix some warnings about unitialized variables. 
git-svn-id: branches/laksen/armiw@29346 -
 2014-12-27 23:11:54 +00:00
Jeppe Johansen
3ad03491ed Add Neg as a pseudo instruction, and fix RRX pseudo code expansion. 
Split some of the thumb code emission rules to make it easier to specify short-cut notations.

git-svn-id: branches/laksen/armiw@29345 -
 2014-12-27 17:44:30 +00:00
Jeppe Johansen
6fff181679 Add support for TBB/TBH instructions. 
Precisize rules for selection of thumb instructions.
Add short-cut notation support for most simple Thumb2 instructions ( add r1,#4 instead of add r1,r1,#4 ).

git-svn-id: branches/laksen/armiw@29343 -
 2014-12-27 16:00:06 +00:00
Jeppe Johansen
71cdedea82 Add missing NOP, and B instruction forms. 
Move ThumbFunc flag from section to symbol.
Make .w forms optional the other way around. If .w is explicitly put on an instruction the assembler should always chose a wide form.

git-svn-id: branches/laksen/armiw@29341 -
 2014-12-27 13:23:02 +00:00
Jeppe Johansen
cc418eef74 Added unified assembler syntax mode so it can be selected with $ASMMODE. 
Fixed bug in Mov instruction.
Added initial scanning of IT/LastInIT detection for proper instruction selection.
Disabled "wide" format flag detection again for now.

git-svn-id: branches/laksen/armiw@29338 -
 2014-12-27 00:19:09 +00:00
Jeppe Johansen
6976af8365 Change .thumb_func to be an ait_directive instead of it's own tai type. 
git-svn-id: branches/laksen/armiw@29334 -
 2014-12-26 23:13:14 +00:00
Jeppe Johansen
9683102813 BL/BLX in thumb mode is a long composed instruction in Thumb as well as Thumb2 
git-svn-id: branches/laksen/armiw@29333 -
 2014-12-26 23:10:34 +00:00
Jeppe Johansen
9227a9fcf2 Reenable check for Wide format flag. 
git-svn-id: branches/laksen/armiw@29331 -
 2014-12-26 20:08:07 +00:00
Jeppe Johansen
5c3093a937 Add most non-VFP Thumb-2 instruction entries for the ARM internal writer. 
git-svn-id: branches/laksen/armiw@29329 -
 2014-12-26 18:35:15 +00:00
Jeppe Johansen
3cb9b30165 Added full 16-bit Thumb support to the ARM internal writer. 
git-svn-id: branches/laksen/armiw@29326 -
 2014-12-25 19:33:14 +00:00
Jeppe Johansen
0494f48bfc Fix capability matrix for ARMv5. It should not have thumb support. 
git-svn-id: branches/laksen/armiw@29287 -
 2014-12-14 16:49:28 +00:00
Jeppe Johansen
901275b4a1 Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen). 
Add missing fields to other elf targets.

git-svn-id: branches/laksen/armiw@29286 -
 2014-12-14 16:28:35 +00:00
Jeppe Johansen
b4a4dda4e5 Make sure to change BLX instructions back to BL when the target is not a Thumb function. 
git-svn-id: branches/laksen/armiw@29282 -
 2014-12-13 18:18:51 +00:00
Jeppe Johansen
fe0cdcfb2e Add a small function to handle encoding of CPU specific ELF flags. This is used to encode EABI version for ARM. 
git-svn-id: branches/laksen/armiw@29281 -
 2014-12-13 17:16:25 +00:00
florian
d540d56908 * unified internal errors 
git-svn-id: trunk@29280 -
 2014-12-13 11:46:59 +00:00
Jeppe Johansen
6c4dbf5a84 Change emission of pre-reloc BLX to BL. 
git-svn-id: branches/laksen/armiw@29278 -
 2014-12-12 23:12:53 +00:00
Jeppe Johansen
387824c1ee Added some APSR register bitmask definitions. 
Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions.
Fixed emission of regsets of S and D registers above 15.
Fixed assembler reader for RRX shiftmode.
There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader.

git-svn-id: branches/laksen/armiw@29277 -
 2014-12-12 22:23:44 +00:00
Jeppe Johansen
414bfba2b2 Emitted instruction was B instead of BL for BL/BLX. 
git-svn-id: branches/laksen/armiw@29262 -
 2014-12-11 22:11:10 +00:00
Jeppe Johansen
e8cb1e198d Forgot to rebuild instruction tables. 
git-svn-id: branches/laksen/armiw@29261 -
 2014-12-11 21:58:05 +00:00
Jeppe Johansen
0b5bcdf439 Modify fixup of BL/BLX instructions and ensure proper form is generated. 
git-svn-id: branches/laksen/armiw@29260 -
 2014-12-11 21:50:44 +00:00
Jeppe Johansen
284a4d9dd7 Encoding of preindexed LDRH/STRH opcodes was missing. 
git-svn-id: branches/laksen/armiw@29254 -
 2014-12-11 11:20:25 +00:00
Jeppe Johansen
b5cd9c048e Small fix for uninitialized variables causing warnings. 
git-svn-id: branches/laksen/armiw@29253 -
 2014-12-11 09:26:48 +00:00
Jeppe Johansen
eb3eaab54b Fix some small encoding bugs. 
git-svn-id: branches/laksen/armiw@29250 -
 2014-12-10 23:28:09 +00:00
Jeppe Johansen
9e5979e8be Implemented UAL syntax support in the ARM assembler reader. Can be toggled with a field for now, but not implemented yet. Still using pre-UAL syntax for now. 
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax.
Updated VFP code in RTL to use UAL syntax too.
Added preliminary ELF support for ARM.
Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target.

git-svn-id: branches/laksen/armiw@29247 -
 2014-12-10 20:44:34 +00:00
Jeppe Johansen
d023c63ad0 Add a lot of instruction table entries and missing instructions for support of most ARM32 mode instructions from ARMv4 up ARMv7A. 
Add some VFP registers.
Rebuilt tables.
Added a lot of VFPv3 and Advanced SIMD(not supported yet) oppostfixes.
Implemented code in aasmcpu to generate binary code from the instructions. Only ARM32 supported so far.

git-svn-id: branches/laksen/armiw@29246 -
 2014-12-10 20:38:23 +00:00
Jeppe Johansen
3bc1db9612 Fixed breakage in the ARM peephole optimizer indirectly brought to light by r29189. 
git-svn-id: trunk@29191 -
 2014-12-01 14:39:40 +00:00
Jeppe Johansen
d04e988ff1 Make sure optimizer don't generate invalid assembler forms (LDRD and STRD). 
git-svn-id: trunk@29189 -
 2014-11-30 17:34:37 +00:00
florian
5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, 
this is an exact operation so it is always allowed
* change only divisions by normal numbers into multiplications

git-svn-id: trunk@29085 -
 2014-11-16 20:47:38 +00:00
Tomas Hajny
3ee3542744 * boolean constant instead of IFDEFs for detection of microcontroller support 
git-svn-id: trunk@29052 -
 2014-11-10 12:34:59 +00:00
Jeppe Johansen
d3e91bb60c Fixed issue #26965. The peephole optimization didn't move a potential register deallocation to after the ldr instruction causing mov's to be removed. 
git-svn-id: trunk@28977 -
 2014-11-03 18:33:32 +00:00
sergei
a3c439c60f - No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up. 
A more radical approach is to remove them altogether. Tested with i386-win32 (the oldest peephole optimizer), mips-linux (the newest one) and arm-linux (the most complex one) targets. The fallout was limited to two minor issues fixed in r28629 and r28708, respectively.

git-svn-id: trunk@28711 -
 2014-09-22 21:33:50 +00:00
sergei
d37e72dbf9 * ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions. 
git-svn-id: trunk@28708 -
 2014-09-22 16:18:16 +00:00
sergei
b08ffa0a87 * ARM: fixed detecting Thumb-style jump tables in insertpcrelativedata() after r28546. 
git-svn-id: trunk@28702 -
 2014-09-21 01:59:25 +00:00
sergei
4a90d7e3de + ARM internal linker: very initial support for Thumb mode, helloworld-class programs compiled with "-Cparmv6m -CIthumb" can now run. 
git-svn-id: trunk@28697 -
 2014-09-19 22:33:37 +00:00
Károly Balogh
1b0a1f4508 ARM: mimic what GNU C does while calling the profiling mcount on ARM 
git-svn-id: trunk@28648 -
 2014-09-13 00:17:10 +00:00
Károly Balogh
739c66291d ARM: first naive attempt to get gprofiling work for arm-linux. (Work-In-Progress, but at least for me it doesn't explode) 
git-svn-id: trunk@28645 -
 2014-09-12 18:51:02 +00:00
florian
3f71b059e5 * improve ldr*/str* handling for arm thumb 
git-svn-id: trunk@28583 -
 2014-09-02 19:37:45 +00:00
florian
2fa7171a45 * generate AND for small set comparisons also when only set vars are involved using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28569 -
 2014-08-31 20:43:13 +00:00
florian
8a7c16327c * fixes reference handling for arm thumb and ldrh, not perfect yet 
git-svn-id: trunk@28568 -
 2014-08-31 18:00:10 +00:00
florian
81c717fc06 + implemented tthumbcgarm.g_external_wrapper in a way which does not destroy lr 
git-svn-id: trunk@28560 -
 2014-08-31 16:35:01 +00:00
florian
dffdde7d53 * fixes reference handling for arm thumb and ldrb, not perfect yet and other ldr/str types might need similiar fixes 
git-svn-id: trunk@28549 -
 2014-08-31 11:37:17 +00:00
florian
db01c50a4f * fixes jump table generate for arm thumb 
git-svn-id: trunk@28546 -
 2014-08-30 22:13:09 +00:00
florian
836a6e46ca * several issues with interface wrappers for thumb fixed 
git-svn-id: trunk@28542 -
 2014-08-30 20:38:26 +00:00
florian
97fc823e33 * generate AND for small set comparions using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28540 -
 2014-08-30 18:02:59 +00:00
florian
09728a9ae2 * improved r28534: LDR/STR on thumb do not support registers >r7 as destination/source 
git-svn-id: trunk@28538 -
 2014-08-30 12:13:00 +00:00
Károly Balogh
5a7b1f00cf ARM: Thumb is an ugly mess, but this at least makes fcl-image package to build with -Ooregvar. someone with more clue is welcomed to review and come up with a better patch. 
git-svn-id: trunk@28534 -
 2014-08-29 17:04:48 +00:00
Károly Balogh
09608a1c28 * fix warnings when compiling the compiler with DFA optimizer enabled on ARM 
git-svn-id: trunk@28498 -
 2014-08-20 13:16:58 +00:00
Jonas Maebe
b18ba8e85b * syncrhonised with trunk up till r28471 
git-svn-id: branches/hlcgllvm@28495 -
 2014-08-19 20:23:11 +00:00
Jonas Maebe
b745dcc64c * moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because 
for some platforms it depends on that routine

git-svn-id: branches/hlcgllvm@28492 -
 2014-08-19 20:22:54 +00:00
Jonas Maebe
e21d31dc99 * fixed compilation with range checking enabled 
git-svn-id: trunk@28447 -
 2014-08-18 20:06:27 +00:00
Jonas Maebe
5c75b6dd6b * synchronised with trunk up till r28402 
git-svn-id: branches/hlcgllvm@28403 -
 2014-08-13 16:04:30 +00:00
Jonas Maebe
c6ddf0001c * simplified in_smallset() and removed some old cruft (there's no need 
anymore to change the register size)

git-svn-id: branches/hlcgllvm@28400 -
 2014-08-12 23:17:45 +00:00
Jonas Maebe
5e280b3131 * don't convert movs into (the non-existing) ldrs in do_spill_replace() 
git-svn-id: trunk@28390 -
 2014-08-12 20:14:24 +00:00
masta
96915b3f0c 16bit Thumb is not able to use tst with an immediate value 
r28315 introduced an arm optimization which requires
  tst rX, #imm
to work. This is not available on 16bit thumb, I've disabled that
optimization on thumb for now.

git-svn-id: trunk@28360 -
 2014-08-10 15:30:44 +00:00
masta
7e22bd53b6 Changed ARMs StrLdr2StrMov peephole optimizer look further ahead 
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.

git-svn-id: trunk@28344 -
 2014-08-08 15:31:10 +00:00
masta
bfa85218fa Introduce TCpuAsmOptimizer.GetNextInstructionUsingRef 
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.

git-svn-id: trunk@28343 -
 2014-08-08 15:31:06 +00:00
masta
d1c5f89976 Make Next an Out-parameter in ARMs GetNextInstructionUsingReg 
The input to Next is not used, reflect that properly.

git-svn-id: trunk@28342 -
 2014-08-08 15:31:01 +00:00
masta
b898b169d4 Fixed 0-cmp optimization in tarmaddnode.second_cmp64bit 
Commit r28315 prevented "= 0" compare-optimizations. Should be fixed now.

git-svn-id: trunk@28317 -
 2014-08-06 15:01:24 +00:00
masta
c88fdb6a4a Add minor optimization for int64 < 0 on arm 
This is a very common construct in normal code and also heavily used in
softfpu code.

The ARM-cg will now just test for the MSB of reghi to be set, instead of
a full comparison against constant 0.

git-svn-id: trunk@28315 -
 2014-08-05 21:31:20 +00:00
masta
7a0c79de60 Fix for AndLsl2Lsl in ARM Peephole optimizer 
AndLsl2Lsl assigned the wrong register to the remaining instruction, and
also did not check for the register.

git-svn-id: trunk@28285 -
 2014-07-31 23:09:33 +00:00
masta
85d208fea4 Fix ARM LoadScheduler in case of Pre/PostIndexed addressing 
There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.

ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2

got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2

and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1

Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1

so r1 got loaded from a modified base-register.

This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.

git-svn-id: trunk@28284 -
 2014-07-31 19:57:09 +00:00
sergei
e4fea2ebc8 * Dummy implementations of a_bit_scan_reg_reg and g_stackpointer_alloc in tcg, removes the need to override these methods in every descendant code generator solely to avoid "constructing a class with abstract method" warning. 
git-svn-id: trunk@28175 -
 2014-07-06 11:34:04 +00:00
Jonas Maebe
7949bebb8d * synchronised with r28168 of trunk 
git-svn-id: branches/hlcgllvm@28169 -
 2014-07-05 21:30:28 +00:00
Jonas Maebe
1516661249 + new chlcgobj class reference variable that can be used to call thlcg* 
virtual methods even when hlcg doesn't contain a valid instance

git-svn-id: branches/hlcgllvm@28143 -
 2014-07-03 22:28:31 +00:00
Jonas Maebe
b0ff41406a * grouped all tai_real* types into a single tai_realconst type, 
to free up space for more ait_* types in taitype (can't have
    more than 32 because they have to fit in a small set)
   o factored out writing of floating point numbers as an array of
     byte in the external assemblers

git-svn-id: branches/hlcgllvm@28105 -
 2014-07-01 16:29:58 +00:00
Jeppe Johansen
857a849173 Added an additional check to the MulAdd2MLA optimization. The operands of the multiplication weren't checked. 
git-svn-id: trunk@28071 -
 2014-06-26 06:05:08 +00:00
Jeppe Johansen
a1197460e1 Constrained a number of optimizations and updated reference offsets for ARM Thumb. 
Embedded target can now build with optimizations.

git-svn-id: trunk@28023 -
 2014-06-21 13:26:33 +00:00
Jeppe Johansen
0dc39b5d63 Applied patch from Michael Ring that adds some startup code for some new stm32f0 and stm32f1 controllers, and fixes naming on some LPC ARMv6m controllers. 
git-svn-id: trunk@28009 -
 2014-06-20 06:49:04 +00:00
masta
0cb1a129b3 {ARM} Implement usage of generic division-by-const optimization 
This utilizes the code commited in r27904 to convert a division by const
into a 32x32->64 bit multiplication for ARM.

git-svn-id: trunk@27929 -
 2014-06-10 20:49:18 +00:00
Jeppe Johansen
96b73b0076 Fixed generation of abs calls for thumb and thumb-2 targets. 
git-svn-id: trunk@27926 -
 2014-06-10 17:48:09 +00:00
Károly Balogh
af95876eba arm: an attempt to improve the a_op_const_ref patch in r27881 
git-svn-id: trunk@27882 -
 2014-06-06 20:48:31 +00:00
Károly Balogh
5b262df7d0 arm: have a CPU specific op_const_ref, so the reference doesn't get fixed up both in a_load_reg_ref and a_load_ref_reg 
git-svn-id: trunk@27881 -
 2014-06-06 17:44:45 +00:00
Jonas Maebe
bacd303208 * synchronized with trunk up to r27758 
git-svn-id: branches/hlcgllvm@27779 -
 2014-05-12 16:12:34 +00:00
sergei
196436b7e7 * ARM: Test if range check of floating point constants is necessary in the same way as on other targets. This should have been part of r10940 6 years ago... 
git-svn-id: trunk@27630 -
 2014-04-22 06:51:54 +00:00
sergei
819f6de01a * ARM: fixed floating point comparison flags for VFP hardfloat (part of Mantis #9362). 
git-svn-id: trunk@27611 -
 2014-04-20 17:06:32 +00:00
sergei
4c3a4646ec * Fixed floating-point comparisons for softfloat targets (part of Mantis #9362). 
git-svn-id: trunk@27584 -
 2014-04-15 23:36:21 +00:00
svenbarth
02495c17bd Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym". 
git-svn-id: trunk@27531 -
 2014-04-11 14:30:59 +00:00
sergei
eeb15fc445 * Added virtual method tprocinfo.postprocess_code and moved target-specific processing from base class into target-specific descendant classes (ARM and AVR, other targets still to do). 
git-svn-id: trunk@27449 -
 2014-04-02 13:14:06 +00:00
Jonas Maebe
d452686c39 * moved pbestrealtype from symdef to symcpu 
git-svn-id: trunk@27441 -
 2014-04-01 21:41:37 +00:00
Jonas Maebe
5053a39501 * moved ARM-specific tprocdef.total_stackframe_size field to cpu-specific 
descendant

git-svn-id: trunk@27437 -
 2014-04-01 21:41:24 +00:00
sergei
68b97bee5a * ARM: Implemented floating-point negation and abs() for softfloat using integer instructions. Fixes webtbs/tw4534.pp, and also yields much faster code than existing implementation. 
Background: these operations are defined as flipping or clearing the upper bit of number, respectively, and never result in precision loss or raise floating-point exceptions.

git-svn-id: trunk@27411 -
 2014-03-31 15:03:15 +00:00
Jonas Maebe
dae5d1ff62 + added class reference types of the architecture-specific t*def/t*sym 
classes

git-svn-id: trunk@27396 -
 2014-03-30 21:04:32 +00:00
florian
8dfcc2b399 * do not reuse tmp. registers in tbasecgarm.handle_load_store 
git-svn-id: trunk@27387 -
 2014-03-30 17:28:45 +00:00
Jonas Maebe
b57c95043f + support overriding tdef/tsym methods with target-specific functionality: 
o made all (non-abstract) tdef and tsym constructors virtual
   o added c*def/c*sym classref types for every (non-abstract) t*def/t*sym
     class
   o added cpusym unit for every architecture that derives a tcpu*def/tcpu*sym
     class from the base classes, and initialises the c*def/c*sym classes with
     them. This is done so that the llvm target will be able to derive from
     the tcpu*def/sym classes without umpteen ifdefs, and it also means that
     the WPO can devirtualise everything because the c* variables are only
     initialised with one class type
   o replaced all t*def/t*sym constructor calls with c*def/c*sym constructor
     calls

git-svn-id: trunk@27361 -
 2014-03-29 22:31:55 +00:00
florian
9464dad2b4 * handle vldr/vstr references with offsets correctly 
git-svn-id: trunk@27273 -
 2014-03-24 19:20:29 +00:00
florian
01b311f6cf * do not insert constant tables on arm thumb in it* sequences 
git-svn-id: trunk@27272 -
 2014-03-24 19:20:01 +00:00
florian
3309254474 * do not write a space before the condition for instructions without operands, not sure why this was there 
git-svn-id: trunk@27268 -
 2014-03-24 17:09:28 +00:00
florian
23c8517418 * applying opXYX2opsXY to ADD makes no sense on thumb-2 (at least as far as I can see) 
git-svn-id: trunk@27267 -
 2014-03-24 17:01:38 +00:00
florian
686a2d2f3f + Support omitting the frame pointer on arm even in procedures with incoming parameters 
on the stack, this can be enabled by -OoFORCENOSTACKFRAME. This reduces the required
  entry/exit code and makes an extra register available to the compiler. However, since this is
  based on an estimation of the required stack size, it might have two drawbacks:
  either the stack frame is estimated to big, the program requires a bigger stack than needed
  or it is estimated too small, then the compiler throws an internalerror during compilation. These
  issues can be overcome as soon as the compiler supports recompiling subroutines if needed.

git-svn-id: trunk@27239 -
 2014-03-23 14:38:53 +00:00
Jonas Maebe
7ea92f48cc * cleaned up do_spill_replace() 
git-svn-id: trunk@27107 -
 2014-03-11 23:19:01 +00:00
Jonas Maebe
45e03d768e * handle ARM PIC jump tables in determining the maximum offset for 
pc-relative loads

git-svn-id: trunk@27105 -
 2014-03-11 23:18:54 +00:00
florian
6deb0b35b5 * handle fpu_vfpv3_d16 properly for thumb2 
git-svn-id: trunk@27102 -
 2014-03-11 21:25:03 +00:00
Jonas Maebe
4065483a50 * completed thlcgobj.location_force_fpureg(), use it everywhere and removed 
ncgutil/thlcg2ll.location_force_fpureg()

git-svn-id: trunk@27071 -
 2014-03-10 09:01:05 +00:00
Jonas Maebe
e9268a0a14 * synchronised with trunk up till r26975 
git-svn-id: branches/hlcgllvm@26976 -
 2014-03-06 21:36:58 +00:00
Jeppe Johansen
95589fb1e2 Apply DataMov2Data to MLA and MLS too. Those have over 4 operands. 
git-svn-id: trunk@26912 -
 2014-03-01 14:21:04 +00:00
florian
ac85d44899 * do OpCmp2OpS optimization also if after cmp follows an appropriate mov 
git-svn-id: trunk@26801 -
 2014-02-16 18:39:55 +00:00
masta
2d2cab0e7a Fix some internalerror codes in the ARM CG 
git-svn-id: trunk@26701 -
 2014-02-07 12:15:08 +00:00
florian
829764e96b + replace registers to spill in mov instructions and convert them into ldr/str 
git-svn-id: trunk@26677 -
 2014-02-05 18:19:41 +00:00
florian
9e4c130bc4 * do not allocate unnecessarily an extra pair of registers when multiplying int64s on arm 
git-svn-id: trunk@26672 -
 2014-02-04 22:02:51 +00:00
Jeppe Johansen
6861cbcf16 Allow FoldShiftLdrStr for all sizes of LDR/STR, and disable it for references that post/pre increment the base register on Thumb-2 targets. 
git-svn-id: trunk@26671 -
 2014-02-04 17:29:13 +00:00
masta
a72a3f4e01 Little cleanup after r26669, no functional changes 
git-svn-id: trunk@26670 -
 2014-02-04 08:04:08 +00:00
masta
80d2ee8ad0 Don't reuse registers on ARM 64 bits shift 
git-svn-id: trunk@26669 -
 2014-02-03 23:47:28 +00:00
sergei
9c1f917e3a * a_call_ref functionality cannot be implemented efficiently at code generator level, because references need specific preparations at earlier points. Moved this support to tcgcallnode and its x86 descendants, and got rid of all ifdef's around. 
+ x86 targets now directly call procedure variables located in references.
- a_call_ref method removed from tcg and thlcgobj.

git-svn-id: trunk@26666 -
 2014-02-03 13:28:56 +00:00
Jeppe Johansen
07b2982e77 Don't do ARM FoldShiftLdrStr peephole optimization if there's an offset in the reference. 
Use UXTH+UXTB instructions instead of two shifts on processors that supports that.
Eliminate internalerror when constant pointers are typecast as arrays.

git-svn-id: trunk@26647 -
 2014-02-01 13:29:35 +00:00
masta
3f8549365a Don't schedule LDRD on ARM 
The load scheduler does not handle LDRD correctly right now, but it does
not prevent A_LDR with PF_D set from beeing scheduled.

git-svn-id: trunk@26637 -
 2014-01-30 21:53:03 +00:00
Jeppe Johansen
257b1affaa Fixed previous fix of LsrAnd2Lsr optimization. 
Added an extra condition for <ARMv6 processors in MLA/MLS optimization.

git-svn-id: trunk@26620 -
 2014-01-29 22:22:58 +00:00
Jeppe Johansen
f773334374 Fixed LsrAnd2Lsr peephole optimization for ARM. 
git-svn-id: trunk@26619 -
 2014-01-29 21:35:28 +00:00
Jeppe Johansen
3b4f59c316 Fixed MLA/MLS peephole optimization and moved it to the generic ARM peephole optimizer. 
git-svn-id: trunk@26613 -
 2014-01-29 17:28:13 +00:00
Jeppe Johansen
184baa3f99 Fixed invalid peephole optimization of ADD/SUB(SP) instructions for ARMv7*M targets. 
git-svn-id: trunk@26612 -
 2014-01-29 17:12:57 +00:00
masta
9e0af11ad8 Rerun the peephole optimizer after removing the current instruction. 
This lets the optimizer pickup on more possible optimizations.

git-svn-id: trunk@26606 -
 2014-01-28 16:00:51 +00:00
masta
57ff589ec7 Always set p to the next instruction after removing p from asml. 
Some time ago we introduced GetNextInstructionUsingReg, which might
return an instruction a couple of instructions away from our current
location. Most of the code then just returned the new instruction (hp1)
instead of the instruction following p. This could prevent the peephole
optimizer from finding possible optimizations.

git-svn-id: trunk@26605 -
 2014-01-28 16:00:47 +00:00
masta
c644503daf Add MovLdr2Ldr peephole optimizer for ARM 
The existing LdrLdr2LdrMov optimizer will generate a lot of
sequences like this:

ldr regA, [...]
mov regB, regA
ldr regB, [regB, ...]

this now gets changed to

ldr regA, [...]
ldr regB, [regA, ...]

this saves an instruction and might open up more possibilities for the load scheduler.

git-svn-id: trunk@26603 -
 2014-01-28 13:20:35 +00:00
masta
77d12f61a2 Handle LDRD and STRD correctly in RegInInstruction for ARM 
LDRD and STRD only have the first even numbered register in their instruction operands,
this additional code will also check for the register following it.
Example:
  ldrd r0, [r13]

The old code will only detect r0 as in use, not the implicit r1.

git-svn-id: trunk@26602 -
 2014-01-28 13:20:26 +00:00
masta
0736bf4ded Try to change typical constant AND-masking operations into shifts for ARM 
If the constant only contains a string of ones starting from lsb or msb
we can shift out the bits accordingly, opening up some possibilities for
the peephole optimizer to fold at least one shift into another
operation.

git-svn-id: trunk@26565 -
 2014-01-22 20:21:02 +00:00
nickysn
85dd9e5789 + added a size parameter to optimize_op_const and do a sign extension of the 'a' parameter up from the specified size, so that things like (i and $ffffffff) get optimized away the same way as (i and -1) 
git-svn-id: trunk@26561 -
 2014-01-22 15:00:34 +00:00
pierre
b158ad6a9c Handle asmextraopt in arm assembler 
git-svn-id: trunk@26545 -
 2014-01-21 00:21:34 +00:00
sergei
a3efd9e1df + Added method taddnode.use_generic_mul64bit, allowing it to inline full 64-bit multiplications, and fixed ARM to comply (it was not checking for possible 32x32 to 64 optimization after detecting a 64-bit operand, so recently added code for 32x32 to 64 bit optimization was inactive). 
git-svn-id: trunk@26500 -
 2014-01-18 09:59:59 +00:00
Jeppe Johansen
123742647c Fixed problem in estimation of stack size for thumb targets. Types passed by value were not handled properly. 
git-svn-id: trunk@26458 -
 2014-01-14 19:27:15 +00:00
masta
fb52392e20 Reformat and comment is_thumb32_imm 
I've just regrouped the conditions a bit for easier understanding. No
functional changes.

git-svn-id: trunk@26449 -
 2014-01-13 21:32:28 +00:00
masta
3ab665e554 Try to split constant XORs into two shiftimms on ARM. 
git-svn-id: trunk@26448 -
 2014-01-13 21:32:24 +00:00
florian
1fc6316cbc * use generic 32*32 -> 64 bit multiplication on arm thumb 
git-svn-id: trunk@26359 -
 2014-01-02 15:23:12 +00:00
masta
bcec29f1b4 Disable generation of UMULL when generating thumb1 code 
git-svn-id: trunk@26355 -
 2014-01-02 13:22:15 +00:00
masta
e5b3d89a5d Add CPUARM_HAS_UMULL flag 
Pre armv4 and all *M variants to not support UMULL and SMULL.

The Flag now gets used for 32x32->64 and 64x64->64 optimized code.

git-svn-id: trunk@26354 -
 2014-01-02 13:06:18 +00:00
masta
f8889e3d6d Use optimize_op_const in ARM cg 
This uses the generic optimizations done in optimize_op_const. Due to
this we can also drop some of the optimizations done in the arm-specific
code.

git-svn-id: trunk@26348 -
 2014-01-01 18:26:42 +00:00
masta
d32abdf047 Little cleanup in tarmaddnode.second_add64bit 
git-svn-id: trunk@26347 -
 2014-01-01 18:26:38 +00:00
masta
cec633e86e Optimized support for 32x32 => 64bit multiplications on ARM 
This code uses UMULL and SMULL to perform the multiplications, which
take two 32bit source registers and two 32bit destination registers.

git-svn-id: trunk@26346 -
 2014-01-01 18:26:29 +00:00
florian
de3a116a28 * handle records with size 0 as function results correctly 
git-svn-id: trunk@26303 -
 2013-12-28 20:19:56 +00:00
florian
561ec1f782 * unified internal errors 
git-svn-id: trunk@26302 -
 2013-12-28 20:19:54 +00:00
Jeppe Johansen
d24cbbf9f5 Changed debug information to dwarf for ARM_embedded, and set local minimum alignment to 4. 
Fixed a bug where ARMv7M targets would not use the DIV instructions.
Moved many size-optimizing Thumb2 peephole optimizations to PostPeepHoleOptsCpu. Previously those optimizations could make it impossible to reuse the shared arm peephole optimizations.
Reenabled a fixed MLA/MLS peephole optimization.
Refactored some FindRegDealloc+regLoadedWithNewValue into RegEndOfLife calls.
Fixed some broken UXTB/UXTH optimizations. Previously they would also match UXT* instructions with ROR shifter ops.

git-svn-id: trunk@26198 -
 2013-12-08 16:50:15 +00:00
Károly Balogh
71e492db1b made arm-linux system unit compilable on anything but Thumb2 after r26161 
git-svn-id: trunk@26175 -
 2013-12-03 16:36:34 +00:00
florian
4d5119bf1c * fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables 
git-svn-id: trunk@26161 -
 2013-12-01 17:02:08 +00:00
sergei
97a706c672 + Add definitions for ELF header flags. 
git-svn-id: trunk@26137 -
 2013-11-25 13:59:12 +00:00
Jonas Maebe
b6d279d4aa * don't transform div-by-power-of-2 into a shift when overflow checking is 
enabled (mantis #23849)

git-svn-id: trunk@26089 -
 2013-11-14 15:47:49 +00:00
Jonas Maebe
25fab5b0b6 + support for array vecnodes on the llvm target, both for regular and for 
bitpacked arrays:
   o separate the element size from the index when constructing the memory
     references, so we can easily use the llvm getelementptr instruction
   o handle conversion of s80real values from their array declaration
     as array elements to floating point values when loading them

git-svn-id: branches/hlcgllvm@26050 -
 2013-11-11 11:16:09 +00:00
Jonas Maebe
5ef93e85b8 + added extra "orgsupreg" parameter to do_spill_read/do_spill_written/ 
do_spill_replace routines, will be necessary by llvm register
    allocator to determine the tdef corresponding to that register
  * replaced uses of taicpu with tai_cpu_abstract_sym in the register
    allocator so that it can work both with taicpu and taillvm instructions

git-svn-id: branches/hlcgllvm@26043 -
 2013-11-11 11:15:43 +00:00
Jonas Maebe
99de108c68 * renamed all paramanagers to tcpuparamanager so the llvm paramanager can 
derive from them without ifdefs

git-svn-id: branches/hlcgllvm@26039 -
 2013-11-11 11:15:27 +00:00
florian
24d88edf37 * fixes arm building after 26004 
git-svn-id: trunk@26012 -
 2013-11-10 17:46:03 +00:00
Károly Balogh
628149d923 support label offsets for ARM like GAS, allows things like ADR r4, .label + 256 
git-svn-id: trunk@25938 -
 2013-11-05 18:10:54 +00:00
Károly Balogh
b67e4fb8b3 added the ADR ARM pseudo instruction to instruction list 
git-svn-id: trunk@25936 -
 2013-11-05 13:16:33 +00:00
Jonas Maebe
555634b755 * (re)set upper bits of register when appropriate for all operations in 
a_op_reg_reg() (except for NOT, which was already handled correctly)
    + test

git-svn-id: trunk@25840 -
 2013-10-22 07:41:52 +00:00
Jonas Maebe
10ae87f11c * fixed LdrLdr2LdrMov optimisation in case the first and second ldr have 
a different size (disable it in that case) + test

git-svn-id: trunk@25778 -
 2013-10-14 12:49:34 +00:00
Jonas Maebe
5276159e77 * correct ofset for saving floating point registers + explanation behind 
the calculation (fixes make cycle on ARMHF)

git-svn-id: trunk@25777 -
 2013-10-14 12:49:31 +00:00
Jonas Maebe
31a3122b91 * fixed LsrAnd2Lsr test by replacing the existing buggy check with comparing 
the outcome of the original and the optimised sequence and seeing whether
    it's same + test

git-svn-id: trunk@25776 -
 2013-10-14 12:49:28 +00:00
sergei
a5ae26da7e * Moved SkipEntryExitMarker method from ARM optimizer to the base one, since it is not target-dependent. Now it can be reused by other targets. 
git-svn-id: trunk@25738 -
 2013-10-10 21:12:49 +00:00
svenbarth
c48d572996 Implement support for saving and restoring address registers. 
cgobj.pas, tcg:
  * g_save_registers: add the amount of used address registers to size as well
  * g_save_registers: save all used address registers
  * g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
  * rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
  * add a saved_address_registers variable with one entry of RS_INVALID

At least a "make fullcycle" did complete.

git-svn-id: trunk@25664 -
 2013-10-05 21:43:42 +00:00
florian
73e6af4864 + cpu flag CPUARM_HAS_THUMB_IDIV 
* test for CPUARM_HAS_THUMB_IDIV instead the CPU type when creating sdiv/udiv code

git-svn-id: trunk@25648 -
 2013-10-05 12:38:55 +00:00
florian
8fb7cf822b * unified internal errors 
git-svn-id: trunk@25647 -
 2013-10-05 12:37:46 +00:00
florian
e0f48b9f02 * calculate stack correction on exit correctly if stack parameters are passed 
git-svn-id: trunk@25427 -
 2013-09-05 21:40:33 +00:00
florian
36e6f99843 * fix tthumbcgarm.g_flags2reg, mov reg,#imm for thumb updates the flags 
git-svn-id: trunk@25426 -
 2013-09-05 21:40:30 +00:00
florian
e2ec3bbcb0 * do shifts for sign/zero extensions correctly 
git-svn-id: trunk@25418 -
 2013-09-04 21:00:46 +00:00
Károly Balogh
2c49af3191 added missing closing parentheses 
git-svn-id: trunk@25413 -
 2013-09-04 14:56:53 +00:00
florian
333e84202f * fixed a_load_reg_reg for thumb 
git-svn-id: trunk@25408 -
 2013-09-03 21:11:02 +00:00
florian
7ef37b5d2a * PLD is not supported by thumb 
git-svn-id: trunk@25407 -
 2013-09-03 21:09:41 +00:00
florian
cb1f38b0af * strd/ldrd are not supported by thumb 
git-svn-id: trunk@25406 -
 2013-09-03 21:09:13 +00:00
Károly Balogh
86cb4d0c12 use a TSuperRegister instead of an aint 
git-svn-id: trunk@25383 -
 2013-08-28 12:58:29 +00:00
Károly Balogh
c677f1fd69 trying harder to follow the code style (no functional changes) 
git-svn-id: trunk@25382 -
 2013-08-28 11:25:15 +00:00
Károly Balogh
25619d4991 removed the const-in-the-left internalerror 
git-svn-id: trunk@25380 -
 2013-08-27 16:18:53 +00:00
Károly Balogh
cb4d01627f save an extra reg if it's required to keep 64bit stack alignment on ARM 
git-svn-id: trunk@25379 -
 2013-08-27 12:49:50 +00:00
masta
ff95d42216 Fix ShiftShift2Shift 1 ARM-peephole optimizer 
The previous code deleted the newly inserted instruction instead of the
existing one, which obviously broke code.

Assembly:
  mov r0, r0, lsr #23
  mov r0, r0, lsr #23

transformed into:
  mov r0, r0, lsr #23

expected was:
  mov r0, #0

The problem only shows up in the very unlikely case of two LSR/ASR or
two LSL following on each other and having a total shift of more than 31
bits.

This fixes test/opt/tarmshift.pp

I've also removed the {%norun} directive from tarmshift.pp as this test
does only make sense when it also runs.

git-svn-id: trunk@25374 -
 2013-08-26 17:41:54 +00:00
florian
d4968e054b + arm: tsettings.instructionset 
* the selected instruction set is now independent from the cpu type: e.g. armv7-a can perfectly execute thumb(2) code

git-svn-id: trunk@25370 -
 2013-08-25 21:56:12 +00:00
florian
7cef301e84 * disable optimization LdrbAnd2Ldrb for arm thumb as it is currently done 
git-svn-id: trunk@25356 -
 2013-08-23 18:41:26 +00:00
florian
f34bee1df7 * arm thumb does not support ror reg1,reg2,#imm 
git-svn-id: trunk@25355 -
 2013-08-23 18:41:24 +00:00
florian
950194678a * handle jump tables correctly when inserting constant pools on arm thumb 
git-svn-id: trunk@25354 -
 2013-08-23 18:41:21 +00:00
Károly Balogh
6591a24bd3 removed some code which must never be called, added an internalerror() instead 
git-svn-id: trunk@25352 -
 2013-08-23 15:58:37 +00:00
florian
e514e84c83 * first_moddivint should not change the return type if div/mul/add is used 
* use create_internal when creating internally add nodes

git-svn-id: trunk@25351 -
 2013-08-23 15:23:00 +00:00
florian
3ebe708574 * do not use r13/r15 for certain data processing operations 
* correct OP_AND with certain types of constants

git-svn-id: trunk@25350 -
 2013-08-23 15:22:58 +00:00
florian
2fe48077b2 * using r13 and r15 is on arm thumb2 also forbidden under certain conditions for the instructions A_SUB,A_AND,A_BIC,A_EOR 
git-svn-id: trunk@25349 -
 2013-08-23 15:22:55 +00:00
florian
d5ddf39f73 * do not do the RedundantMovProcess optimization when the involved registers are r13 or r15 and if the target is arm thumb(2) 
git-svn-id: trunk@25348 -
 2013-08-23 15:22:53 +00:00
florian
b4c7b40049 * do not split statements following A_IT* instructions on arm thumb2 when inserting constant pools 
git-svn-id: trunk@25347 -
 2013-08-23 15:22:51 +00:00
florian
8884f1c0bf * arm thumb2 supports only left shifted index registers up to 3 bits 
git-svn-id: trunk@25346 -
 2013-08-23 15:22:49 +00:00
florian
6df2917d93 * fix spilling of vfp instructions 
* spelling mistake fixed

git-svn-id: trunk@25345 -
 2013-08-23 15:22:46 +00:00
florian
c350c3a5e4 * arm thumb2 does not understand tst reg1,reg2,lsl reg3 
git-svn-id: trunk@25344 -
 2013-08-23 15:22:44 +00:00
florian
bb73a2891b * prevent generation of mul/mla statements with illegal registers 
git-svn-id: trunk@25343 -
 2013-08-23 15:22:41 +00:00
Jonas Maebe
4ec9ec2009 + PIC support for Darwin/ARM: 
o does not use GOT
   o enabled by default like for other Darwin platforms
  - removed Darwin/ARM call stub support: no longer needed with current
    Xcode versions (at least Xcode 4.2+), and we didn't support PIC
    in them yet

git-svn-id: trunk@25325 -
 2013-08-22 08:14:24 +00:00
Jonas Maebe
8ffb704b8c * don't split address labels from the instruction they belong with when 
rescheduling (needed for GOT-less PIC)

git-svn-id: trunk@25324 -
 2013-08-22 08:14:18 +00:00
Jonas Maebe
b31e5c2536 + PIC support for ARM jump tables (only for plain ARM right now, not 
yet for thumb/thumb2)

git-svn-id: trunk@25323 -
 2013-08-21 22:28:24 +00:00
florian
6606955b88 + basic support for pic on arm-linux 
git-svn-id: trunk@25297 -
 2013-08-19 21:35:37 +00:00