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1161 Commits

Author SHA1 Message Date
florian
5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, 
this is an exact operation so it is always allowed
* change only divisions by normal numbers into multiplications

git-svn-id: trunk@29085 -
 2014-11-16 20:47:38 +00:00
Tomas Hajny
3ee3542744 * boolean constant instead of IFDEFs for detection of microcontroller support 
git-svn-id: trunk@29052 -
 2014-11-10 12:34:59 +00:00
Jeppe Johansen
d3e91bb60c Fixed issue #26965. The peephole optimization didn't move a potential register deallocation to after the ldr instruction causing mov's to be removed. 
git-svn-id: trunk@28977 -
 2014-11-03 18:33:32 +00:00
sergei
a3c439c60f - No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up. 
A more radical approach is to remove them altogether. Tested with i386-win32 (the oldest peephole optimizer), mips-linux (the newest one) and arm-linux (the most complex one) targets. The fallout was limited to two minor issues fixed in r28629 and r28708, respectively.

git-svn-id: trunk@28711 -
 2014-09-22 21:33:50 +00:00
sergei
d37e72dbf9 * ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions. 
git-svn-id: trunk@28708 -
 2014-09-22 16:18:16 +00:00
sergei
b08ffa0a87 * ARM: fixed detecting Thumb-style jump tables in insertpcrelativedata() after r28546. 
git-svn-id: trunk@28702 -
 2014-09-21 01:59:25 +00:00
sergei
4a90d7e3de + ARM internal linker: very initial support for Thumb mode, helloworld-class programs compiled with "-Cparmv6m -CIthumb" can now run. 
git-svn-id: trunk@28697 -
 2014-09-19 22:33:37 +00:00
Károly Balogh
1b0a1f4508 ARM: mimic what GNU C does while calling the profiling mcount on ARM 
git-svn-id: trunk@28648 -
 2014-09-13 00:17:10 +00:00
Károly Balogh
739c66291d ARM: first naive attempt to get gprofiling work for arm-linux. (Work-In-Progress, but at least for me it doesn't explode) 
git-svn-id: trunk@28645 -
 2014-09-12 18:51:02 +00:00
florian
3f71b059e5 * improve ldr*/str* handling for arm thumb 
git-svn-id: trunk@28583 -
 2014-09-02 19:37:45 +00:00
florian
2fa7171a45 * generate AND for small set comparisons also when only set vars are involved using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28569 -
 2014-08-31 20:43:13 +00:00
florian
8a7c16327c * fixes reference handling for arm thumb and ldrh, not perfect yet 
git-svn-id: trunk@28568 -
 2014-08-31 18:00:10 +00:00
florian
81c717fc06 + implemented tthumbcgarm.g_external_wrapper in a way which does not destroy lr 
git-svn-id: trunk@28560 -
 2014-08-31 16:35:01 +00:00
florian
dffdde7d53 * fixes reference handling for arm thumb and ldrb, not perfect yet and other ldr/str types might need similiar fixes 
git-svn-id: trunk@28549 -
 2014-08-31 11:37:17 +00:00
florian
db01c50a4f * fixes jump table generate for arm thumb 
git-svn-id: trunk@28546 -
 2014-08-30 22:13:09 +00:00
florian
836a6e46ca * several issues with interface wrappers for thumb fixed 
git-svn-id: trunk@28542 -
 2014-08-30 20:38:26 +00:00
florian
97fc823e33 * generate AND for small set comparions using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28540 -
 2014-08-30 18:02:59 +00:00
florian
09728a9ae2 * improved r28534: LDR/STR on thumb do not support registers >r7 as destination/source 
git-svn-id: trunk@28538 -
 2014-08-30 12:13:00 +00:00
Károly Balogh
5a7b1f00cf ARM: Thumb is an ugly mess, but this at least makes fcl-image package to build with -Ooregvar. someone with more clue is welcomed to review and come up with a better patch. 
git-svn-id: trunk@28534 -
 2014-08-29 17:04:48 +00:00
Károly Balogh
09608a1c28 * fix warnings when compiling the compiler with DFA optimizer enabled on ARM 
git-svn-id: trunk@28498 -
 2014-08-20 13:16:58 +00:00
Jonas Maebe
b18ba8e85b * syncrhonised with trunk up till r28471 
git-svn-id: branches/hlcgllvm@28495 -
 2014-08-19 20:23:11 +00:00
Jonas Maebe
b745dcc64c * moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because 
for some platforms it depends on that routine

git-svn-id: branches/hlcgllvm@28492 -
 2014-08-19 20:22:54 +00:00
Jonas Maebe
e21d31dc99 * fixed compilation with range checking enabled 
git-svn-id: trunk@28447 -
 2014-08-18 20:06:27 +00:00
Jonas Maebe
5c75b6dd6b * synchronised with trunk up till r28402 
git-svn-id: branches/hlcgllvm@28403 -
 2014-08-13 16:04:30 +00:00
Jonas Maebe
c6ddf0001c * simplified in_smallset() and removed some old cruft (there's no need 
anymore to change the register size)

git-svn-id: branches/hlcgllvm@28400 -
 2014-08-12 23:17:45 +00:00
Jonas Maebe
5e280b3131 * don't convert movs into (the non-existing) ldrs in do_spill_replace() 
git-svn-id: trunk@28390 -
 2014-08-12 20:14:24 +00:00
masta
96915b3f0c 16bit Thumb is not able to use tst with an immediate value 
r28315 introduced an arm optimization which requires
  tst rX, #imm
to work. This is not available on 16bit thumb, I've disabled that
optimization on thumb for now.

git-svn-id: trunk@28360 -
 2014-08-10 15:30:44 +00:00
masta
7e22bd53b6 Changed ARMs StrLdr2StrMov peephole optimizer look further ahead 
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.

git-svn-id: trunk@28344 -
 2014-08-08 15:31:10 +00:00
masta
bfa85218fa Introduce TCpuAsmOptimizer.GetNextInstructionUsingRef 
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.

git-svn-id: trunk@28343 -
 2014-08-08 15:31:06 +00:00
masta
d1c5f89976 Make Next an Out-parameter in ARMs GetNextInstructionUsingReg 
The input to Next is not used, reflect that properly.

git-svn-id: trunk@28342 -
 2014-08-08 15:31:01 +00:00
masta
b898b169d4 Fixed 0-cmp optimization in tarmaddnode.second_cmp64bit 
Commit r28315 prevented "= 0" compare-optimizations. Should be fixed now.

git-svn-id: trunk@28317 -
 2014-08-06 15:01:24 +00:00
masta
c88fdb6a4a Add minor optimization for int64 < 0 on arm 
This is a very common construct in normal code and also heavily used in
softfpu code.

The ARM-cg will now just test for the MSB of reghi to be set, instead of
a full comparison against constant 0.

git-svn-id: trunk@28315 -
 2014-08-05 21:31:20 +00:00
masta
7a0c79de60 Fix for AndLsl2Lsl in ARM Peephole optimizer 
AndLsl2Lsl assigned the wrong register to the remaining instruction, and
also did not check for the register.

git-svn-id: trunk@28285 -
 2014-07-31 23:09:33 +00:00
masta
85d208fea4 Fix ARM LoadScheduler in case of Pre/PostIndexed addressing 
There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.

ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2

got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2

and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1

Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1

so r1 got loaded from a modified base-register.

This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.

git-svn-id: trunk@28284 -
 2014-07-31 19:57:09 +00:00
sergei
e4fea2ebc8 * Dummy implementations of a_bit_scan_reg_reg and g_stackpointer_alloc in tcg, removes the need to override these methods in every descendant code generator solely to avoid "constructing a class with abstract method" warning. 
git-svn-id: trunk@28175 -
 2014-07-06 11:34:04 +00:00
Jonas Maebe
7949bebb8d * synchronised with r28168 of trunk 
git-svn-id: branches/hlcgllvm@28169 -
 2014-07-05 21:30:28 +00:00
Jonas Maebe
1516661249 + new chlcgobj class reference variable that can be used to call thlcg* 
virtual methods even when hlcg doesn't contain a valid instance

git-svn-id: branches/hlcgllvm@28143 -
 2014-07-03 22:28:31 +00:00
Jonas Maebe
b0ff41406a * grouped all tai_real* types into a single tai_realconst type, 
to free up space for more ait_* types in taitype (can't have
    more than 32 because they have to fit in a small set)
   o factored out writing of floating point numbers as an array of
     byte in the external assemblers

git-svn-id: branches/hlcgllvm@28105 -
 2014-07-01 16:29:58 +00:00
Jeppe Johansen
857a849173 Added an additional check to the MulAdd2MLA optimization. The operands of the multiplication weren't checked. 
git-svn-id: trunk@28071 -
 2014-06-26 06:05:08 +00:00
Jeppe Johansen
a1197460e1 Constrained a number of optimizations and updated reference offsets for ARM Thumb. 
Embedded target can now build with optimizations.

git-svn-id: trunk@28023 -
 2014-06-21 13:26:33 +00:00
Jeppe Johansen
0dc39b5d63 Applied patch from Michael Ring that adds some startup code for some new stm32f0 and stm32f1 controllers, and fixes naming on some LPC ARMv6m controllers. 
git-svn-id: trunk@28009 -
 2014-06-20 06:49:04 +00:00
masta
0cb1a129b3 {ARM} Implement usage of generic division-by-const optimization 
This utilizes the code commited in r27904 to convert a division by const
into a 32x32->64 bit multiplication for ARM.

git-svn-id: trunk@27929 -
 2014-06-10 20:49:18 +00:00
Jeppe Johansen
96b73b0076 Fixed generation of abs calls for thumb and thumb-2 targets. 
git-svn-id: trunk@27926 -
 2014-06-10 17:48:09 +00:00
Károly Balogh
af95876eba arm: an attempt to improve the a_op_const_ref patch in r27881 
git-svn-id: trunk@27882 -
 2014-06-06 20:48:31 +00:00
Károly Balogh
5b262df7d0 arm: have a CPU specific op_const_ref, so the reference doesn't get fixed up both in a_load_reg_ref and a_load_ref_reg 
git-svn-id: trunk@27881 -
 2014-06-06 17:44:45 +00:00
Jonas Maebe
bacd303208 * synchronized with trunk up to r27758 
git-svn-id: branches/hlcgllvm@27779 -
 2014-05-12 16:12:34 +00:00
sergei
196436b7e7 * ARM: Test if range check of floating point constants is necessary in the same way as on other targets. This should have been part of r10940 6 years ago... 
git-svn-id: trunk@27630 -
 2014-04-22 06:51:54 +00:00
sergei
819f6de01a * ARM: fixed floating point comparison flags for VFP hardfloat (part of Mantis #9362). 
git-svn-id: trunk@27611 -
 2014-04-20 17:06:32 +00:00
sergei
4c3a4646ec * Fixed floating-point comparisons for softfloat targets (part of Mantis #9362). 
git-svn-id: trunk@27584 -
 2014-04-15 23:36:21 +00:00
svenbarth
02495c17bd Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym". 
git-svn-id: trunk@27531 -
 2014-04-11 14:30:59 +00:00
sergei
eeb15fc445 * Added virtual method tprocinfo.postprocess_code and moved target-specific processing from base class into target-specific descendant classes (ARM and AVR, other targets still to do). 
git-svn-id: trunk@27449 -
 2014-04-02 13:14:06 +00:00
Jonas Maebe
d452686c39 * moved pbestrealtype from symdef to symcpu 
git-svn-id: trunk@27441 -
 2014-04-01 21:41:37 +00:00
Jonas Maebe
5053a39501 * moved ARM-specific tprocdef.total_stackframe_size field to cpu-specific 
descendant

git-svn-id: trunk@27437 -
 2014-04-01 21:41:24 +00:00
sergei
68b97bee5a * ARM: Implemented floating-point negation and abs() for softfloat using integer instructions. Fixes webtbs/tw4534.pp, and also yields much faster code than existing implementation. 
Background: these operations are defined as flipping or clearing the upper bit of number, respectively, and never result in precision loss or raise floating-point exceptions.

git-svn-id: trunk@27411 -
 2014-03-31 15:03:15 +00:00
Jonas Maebe
dae5d1ff62 + added class reference types of the architecture-specific t*def/t*sym 
classes

git-svn-id: trunk@27396 -
 2014-03-30 21:04:32 +00:00
florian
8dfcc2b399 * do not reuse tmp. registers in tbasecgarm.handle_load_store 
git-svn-id: trunk@27387 -
 2014-03-30 17:28:45 +00:00
Jonas Maebe
b57c95043f + support overriding tdef/tsym methods with target-specific functionality: 
o made all (non-abstract) tdef and tsym constructors virtual
   o added c*def/c*sym classref types for every (non-abstract) t*def/t*sym
     class
   o added cpusym unit for every architecture that derives a tcpu*def/tcpu*sym
     class from the base classes, and initialises the c*def/c*sym classes with
     them. This is done so that the llvm target will be able to derive from
     the tcpu*def/sym classes without umpteen ifdefs, and it also means that
     the WPO can devirtualise everything because the c* variables are only
     initialised with one class type
   o replaced all t*def/t*sym constructor calls with c*def/c*sym constructor
     calls

git-svn-id: trunk@27361 -
 2014-03-29 22:31:55 +00:00
florian
9464dad2b4 * handle vldr/vstr references with offsets correctly 
git-svn-id: trunk@27273 -
 2014-03-24 19:20:29 +00:00
florian
01b311f6cf * do not insert constant tables on arm thumb in it* sequences 
git-svn-id: trunk@27272 -
 2014-03-24 19:20:01 +00:00
florian
3309254474 * do not write a space before the condition for instructions without operands, not sure why this was there 
git-svn-id: trunk@27268 -
 2014-03-24 17:09:28 +00:00
florian
23c8517418 * applying opXYX2opsXY to ADD makes no sense on thumb-2 (at least as far as I can see) 
git-svn-id: trunk@27267 -
 2014-03-24 17:01:38 +00:00
florian
686a2d2f3f + Support omitting the frame pointer on arm even in procedures with incoming parameters 
on the stack, this can be enabled by -OoFORCENOSTACKFRAME. This reduces the required
  entry/exit code and makes an extra register available to the compiler. However, since this is
  based on an estimation of the required stack size, it might have two drawbacks:
  either the stack frame is estimated to big, the program requires a bigger stack than needed
  or it is estimated too small, then the compiler throws an internalerror during compilation. These
  issues can be overcome as soon as the compiler supports recompiling subroutines if needed.

git-svn-id: trunk@27239 -
 2014-03-23 14:38:53 +00:00
Jonas Maebe
7ea92f48cc * cleaned up do_spill_replace() 
git-svn-id: trunk@27107 -
 2014-03-11 23:19:01 +00:00
Jonas Maebe
45e03d768e * handle ARM PIC jump tables in determining the maximum offset for 
pc-relative loads

git-svn-id: trunk@27105 -
 2014-03-11 23:18:54 +00:00
florian
6deb0b35b5 * handle fpu_vfpv3_d16 properly for thumb2 
git-svn-id: trunk@27102 -
 2014-03-11 21:25:03 +00:00
Jonas Maebe
4065483a50 * completed thlcgobj.location_force_fpureg(), use it everywhere and removed 
ncgutil/thlcg2ll.location_force_fpureg()

git-svn-id: trunk@27071 -
 2014-03-10 09:01:05 +00:00
Jonas Maebe
e9268a0a14 * synchronised with trunk up till r26975 
git-svn-id: branches/hlcgllvm@26976 -
 2014-03-06 21:36:58 +00:00
Jeppe Johansen
95589fb1e2 Apply DataMov2Data to MLA and MLS too. Those have over 4 operands. 
git-svn-id: trunk@26912 -
 2014-03-01 14:21:04 +00:00
florian
ac85d44899 * do OpCmp2OpS optimization also if after cmp follows an appropriate mov 
git-svn-id: trunk@26801 -
 2014-02-16 18:39:55 +00:00
masta
2d2cab0e7a Fix some internalerror codes in the ARM CG 
git-svn-id: trunk@26701 -
 2014-02-07 12:15:08 +00:00
florian
829764e96b + replace registers to spill in mov instructions and convert them into ldr/str 
git-svn-id: trunk@26677 -
 2014-02-05 18:19:41 +00:00
florian
9e4c130bc4 * do not allocate unnecessarily an extra pair of registers when multiplying int64s on arm 
git-svn-id: trunk@26672 -
 2014-02-04 22:02:51 +00:00
Jeppe Johansen
6861cbcf16 Allow FoldShiftLdrStr for all sizes of LDR/STR, and disable it for references that post/pre increment the base register on Thumb-2 targets. 
git-svn-id: trunk@26671 -
 2014-02-04 17:29:13 +00:00
masta
a72a3f4e01 Little cleanup after r26669, no functional changes 
git-svn-id: trunk@26670 -
 2014-02-04 08:04:08 +00:00
masta
80d2ee8ad0 Don't reuse registers on ARM 64 bits shift 
git-svn-id: trunk@26669 -
 2014-02-03 23:47:28 +00:00
sergei
9c1f917e3a * a_call_ref functionality cannot be implemented efficiently at code generator level, because references need specific preparations at earlier points. Moved this support to tcgcallnode and its x86 descendants, and got rid of all ifdef's around. 
+ x86 targets now directly call procedure variables located in references.
- a_call_ref method removed from tcg and thlcgobj.

git-svn-id: trunk@26666 -
 2014-02-03 13:28:56 +00:00
Jeppe Johansen
07b2982e77 Don't do ARM FoldShiftLdrStr peephole optimization if there's an offset in the reference. 
Use UXTH+UXTB instructions instead of two shifts on processors that supports that.
Eliminate internalerror when constant pointers are typecast as arrays.

git-svn-id: trunk@26647 -
 2014-02-01 13:29:35 +00:00
masta
3f8549365a Don't schedule LDRD on ARM 
The load scheduler does not handle LDRD correctly right now, but it does
not prevent A_LDR with PF_D set from beeing scheduled.

git-svn-id: trunk@26637 -
 2014-01-30 21:53:03 +00:00
Jeppe Johansen
257b1affaa Fixed previous fix of LsrAnd2Lsr optimization. 
Added an extra condition for <ARMv6 processors in MLA/MLS optimization.

git-svn-id: trunk@26620 -
 2014-01-29 22:22:58 +00:00
Jeppe Johansen
f773334374 Fixed LsrAnd2Lsr peephole optimization for ARM. 
git-svn-id: trunk@26619 -
 2014-01-29 21:35:28 +00:00
Jeppe Johansen
3b4f59c316 Fixed MLA/MLS peephole optimization and moved it to the generic ARM peephole optimizer. 
git-svn-id: trunk@26613 -
 2014-01-29 17:28:13 +00:00
Jeppe Johansen
184baa3f99 Fixed invalid peephole optimization of ADD/SUB(SP) instructions for ARMv7*M targets. 
git-svn-id: trunk@26612 -
 2014-01-29 17:12:57 +00:00
masta
9e0af11ad8 Rerun the peephole optimizer after removing the current instruction. 
This lets the optimizer pickup on more possible optimizations.

git-svn-id: trunk@26606 -
 2014-01-28 16:00:51 +00:00
masta
57ff589ec7 Always set p to the next instruction after removing p from asml. 
Some time ago we introduced GetNextInstructionUsingReg, which might
return an instruction a couple of instructions away from our current
location. Most of the code then just returned the new instruction (hp1)
instead of the instruction following p. This could prevent the peephole
optimizer from finding possible optimizations.

git-svn-id: trunk@26605 -
 2014-01-28 16:00:47 +00:00
masta
c644503daf Add MovLdr2Ldr peephole optimizer for ARM 
The existing LdrLdr2LdrMov optimizer will generate a lot of
sequences like this:

ldr regA, [...]
mov regB, regA
ldr regB, [regB, ...]

this now gets changed to

ldr regA, [...]
ldr regB, [regA, ...]

this saves an instruction and might open up more possibilities for the load scheduler.

git-svn-id: trunk@26603 -
 2014-01-28 13:20:35 +00:00
masta
77d12f61a2 Handle LDRD and STRD correctly in RegInInstruction for ARM 
LDRD and STRD only have the first even numbered register in their instruction operands,
this additional code will also check for the register following it.
Example:
  ldrd r0, [r13]

The old code will only detect r0 as in use, not the implicit r1.

git-svn-id: trunk@26602 -
 2014-01-28 13:20:26 +00:00
masta
0736bf4ded Try to change typical constant AND-masking operations into shifts for ARM 
If the constant only contains a string of ones starting from lsb or msb
we can shift out the bits accordingly, opening up some possibilities for
the peephole optimizer to fold at least one shift into another
operation.

git-svn-id: trunk@26565 -
 2014-01-22 20:21:02 +00:00
nickysn
85dd9e5789 + added a size parameter to optimize_op_const and do a sign extension of the 'a' parameter up from the specified size, so that things like (i and $ffffffff) get optimized away the same way as (i and -1) 
git-svn-id: trunk@26561 -
 2014-01-22 15:00:34 +00:00
pierre
b158ad6a9c Handle asmextraopt in arm assembler 
git-svn-id: trunk@26545 -
 2014-01-21 00:21:34 +00:00
sergei
a3efd9e1df + Added method taddnode.use_generic_mul64bit, allowing it to inline full 64-bit multiplications, and fixed ARM to comply (it was not checking for possible 32x32 to 64 optimization after detecting a 64-bit operand, so recently added code for 32x32 to 64 bit optimization was inactive). 
git-svn-id: trunk@26500 -
 2014-01-18 09:59:59 +00:00
Jeppe Johansen
123742647c Fixed problem in estimation of stack size for thumb targets. Types passed by value were not handled properly. 
git-svn-id: trunk@26458 -
 2014-01-14 19:27:15 +00:00
masta
fb52392e20 Reformat and comment is_thumb32_imm 
I've just regrouped the conditions a bit for easier understanding. No
functional changes.

git-svn-id: trunk@26449 -
 2014-01-13 21:32:28 +00:00
masta
3ab665e554 Try to split constant XORs into two shiftimms on ARM. 
git-svn-id: trunk@26448 -
 2014-01-13 21:32:24 +00:00
florian
1fc6316cbc * use generic 32*32 -> 64 bit multiplication on arm thumb 
git-svn-id: trunk@26359 -
 2014-01-02 15:23:12 +00:00
masta
bcec29f1b4 Disable generation of UMULL when generating thumb1 code 
git-svn-id: trunk@26355 -
 2014-01-02 13:22:15 +00:00
masta
e5b3d89a5d Add CPUARM_HAS_UMULL flag 
Pre armv4 and all *M variants to not support UMULL and SMULL.

The Flag now gets used for 32x32->64 and 64x64->64 optimized code.

git-svn-id: trunk@26354 -
 2014-01-02 13:06:18 +00:00
masta
f8889e3d6d Use optimize_op_const in ARM cg 
This uses the generic optimizations done in optimize_op_const. Due to
this we can also drop some of the optimizations done in the arm-specific
code.

git-svn-id: trunk@26348 -
 2014-01-01 18:26:42 +00:00
masta
d32abdf047 Little cleanup in tarmaddnode.second_add64bit 
git-svn-id: trunk@26347 -
 2014-01-01 18:26:38 +00:00
masta
cec633e86e Optimized support for 32x32 => 64bit multiplications on ARM 
This code uses UMULL and SMULL to perform the multiplications, which
take two 32bit source registers and two 32bit destination registers.

git-svn-id: trunk@26346 -
 2014-01-01 18:26:29 +00:00
florian
de3a116a28 * handle records with size 0 as function results correctly 
git-svn-id: trunk@26303 -
 2013-12-28 20:19:56 +00:00
florian
561ec1f782 * unified internal errors 
git-svn-id: trunk@26302 -
 2013-12-28 20:19:54 +00:00
Jeppe Johansen
d24cbbf9f5 Changed debug information to dwarf for ARM_embedded, and set local minimum alignment to 4. 
Fixed a bug where ARMv7M targets would not use the DIV instructions.
Moved many size-optimizing Thumb2 peephole optimizations to PostPeepHoleOptsCpu. Previously those optimizations could make it impossible to reuse the shared arm peephole optimizations.
Reenabled a fixed MLA/MLS peephole optimization.
Refactored some FindRegDealloc+regLoadedWithNewValue into RegEndOfLife calls.
Fixed some broken UXTB/UXTH optimizations. Previously they would also match UXT* instructions with ROR shifter ops.

git-svn-id: trunk@26198 -
 2013-12-08 16:50:15 +00:00
Károly Balogh
71e492db1b made arm-linux system unit compilable on anything but Thumb2 after r26161 
git-svn-id: trunk@26175 -
 2013-12-03 16:36:34 +00:00
florian
4d5119bf1c * fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables 
git-svn-id: trunk@26161 -
 2013-12-01 17:02:08 +00:00
sergei
97a706c672 + Add definitions for ELF header flags. 
git-svn-id: trunk@26137 -
 2013-11-25 13:59:12 +00:00
Jonas Maebe
b6d279d4aa * don't transform div-by-power-of-2 into a shift when overflow checking is 
enabled (mantis #23849)

git-svn-id: trunk@26089 -
 2013-11-14 15:47:49 +00:00
Jonas Maebe
25fab5b0b6 + support for array vecnodes on the llvm target, both for regular and for 
bitpacked arrays:
   o separate the element size from the index when constructing the memory
     references, so we can easily use the llvm getelementptr instruction
   o handle conversion of s80real values from their array declaration
     as array elements to floating point values when loading them

git-svn-id: branches/hlcgllvm@26050 -
 2013-11-11 11:16:09 +00:00
Jonas Maebe
5ef93e85b8 + added extra "orgsupreg" parameter to do_spill_read/do_spill_written/ 
do_spill_replace routines, will be necessary by llvm register
    allocator to determine the tdef corresponding to that register
  * replaced uses of taicpu with tai_cpu_abstract_sym in the register
    allocator so that it can work both with taicpu and taillvm instructions

git-svn-id: branches/hlcgllvm@26043 -
 2013-11-11 11:15:43 +00:00
Jonas Maebe
99de108c68 * renamed all paramanagers to tcpuparamanager so the llvm paramanager can 
derive from them without ifdefs

git-svn-id: branches/hlcgllvm@26039 -
 2013-11-11 11:15:27 +00:00
florian
24d88edf37 * fixes arm building after 26004 
git-svn-id: trunk@26012 -
 2013-11-10 17:46:03 +00:00
Károly Balogh
628149d923 support label offsets for ARM like GAS, allows things like ADR r4, .label + 256 
git-svn-id: trunk@25938 -
 2013-11-05 18:10:54 +00:00
Károly Balogh
b67e4fb8b3 added the ADR ARM pseudo instruction to instruction list 
git-svn-id: trunk@25936 -
 2013-11-05 13:16:33 +00:00
Jonas Maebe
555634b755 * (re)set upper bits of register when appropriate for all operations in 
a_op_reg_reg() (except for NOT, which was already handled correctly)
    + test

git-svn-id: trunk@25840 -
 2013-10-22 07:41:52 +00:00
Jonas Maebe
10ae87f11c * fixed LdrLdr2LdrMov optimisation in case the first and second ldr have 
a different size (disable it in that case) + test

git-svn-id: trunk@25778 -
 2013-10-14 12:49:34 +00:00
Jonas Maebe
5276159e77 * correct ofset for saving floating point registers + explanation behind 
the calculation (fixes make cycle on ARMHF)

git-svn-id: trunk@25777 -
 2013-10-14 12:49:31 +00:00
Jonas Maebe
31a3122b91 * fixed LsrAnd2Lsr test by replacing the existing buggy check with comparing 
the outcome of the original and the optimised sequence and seeing whether
    it's same + test

git-svn-id: trunk@25776 -
 2013-10-14 12:49:28 +00:00
sergei
a5ae26da7e * Moved SkipEntryExitMarker method from ARM optimizer to the base one, since it is not target-dependent. Now it can be reused by other targets. 
git-svn-id: trunk@25738 -
 2013-10-10 21:12:49 +00:00
svenbarth
c48d572996 Implement support for saving and restoring address registers. 
cgobj.pas, tcg:
  * g_save_registers: add the amount of used address registers to size as well
  * g_save_registers: save all used address registers
  * g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
  * rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
  * add a saved_address_registers variable with one entry of RS_INVALID

At least a "make fullcycle" did complete.

git-svn-id: trunk@25664 -
 2013-10-05 21:43:42 +00:00
florian
73e6af4864 + cpu flag CPUARM_HAS_THUMB_IDIV 
* test for CPUARM_HAS_THUMB_IDIV instead the CPU type when creating sdiv/udiv code

git-svn-id: trunk@25648 -
 2013-10-05 12:38:55 +00:00
florian
8fb7cf822b * unified internal errors 
git-svn-id: trunk@25647 -
 2013-10-05 12:37:46 +00:00
florian
e0f48b9f02 * calculate stack correction on exit correctly if stack parameters are passed 
git-svn-id: trunk@25427 -
 2013-09-05 21:40:33 +00:00
florian
36e6f99843 * fix tthumbcgarm.g_flags2reg, mov reg,#imm for thumb updates the flags 
git-svn-id: trunk@25426 -
 2013-09-05 21:40:30 +00:00
florian
e2ec3bbcb0 * do shifts for sign/zero extensions correctly 
git-svn-id: trunk@25418 -
 2013-09-04 21:00:46 +00:00
Károly Balogh
2c49af3191 added missing closing parentheses 
git-svn-id: trunk@25413 -
 2013-09-04 14:56:53 +00:00
florian
333e84202f * fixed a_load_reg_reg for thumb 
git-svn-id: trunk@25408 -
 2013-09-03 21:11:02 +00:00
florian
7ef37b5d2a * PLD is not supported by thumb 
git-svn-id: trunk@25407 -
 2013-09-03 21:09:41 +00:00
florian
cb1f38b0af * strd/ldrd are not supported by thumb 
git-svn-id: trunk@25406 -
 2013-09-03 21:09:13 +00:00
Károly Balogh
86cb4d0c12 use a TSuperRegister instead of an aint 
git-svn-id: trunk@25383 -
 2013-08-28 12:58:29 +00:00
Károly Balogh
c677f1fd69 trying harder to follow the code style (no functional changes) 
git-svn-id: trunk@25382 -
 2013-08-28 11:25:15 +00:00
Károly Balogh
25619d4991 removed the const-in-the-left internalerror 
git-svn-id: trunk@25380 -
 2013-08-27 16:18:53 +00:00
Károly Balogh
cb4d01627f save an extra reg if it's required to keep 64bit stack alignment on ARM 
git-svn-id: trunk@25379 -
 2013-08-27 12:49:50 +00:00
masta
ff95d42216 Fix ShiftShift2Shift 1 ARM-peephole optimizer 
The previous code deleted the newly inserted instruction instead of the
existing one, which obviously broke code.

Assembly:
  mov r0, r0, lsr #23
  mov r0, r0, lsr #23

transformed into:
  mov r0, r0, lsr #23

expected was:
  mov r0, #0

The problem only shows up in the very unlikely case of two LSR/ASR or
two LSL following on each other and having a total shift of more than 31
bits.

This fixes test/opt/tarmshift.pp

I've also removed the {%norun} directive from tarmshift.pp as this test
does only make sense when it also runs.

git-svn-id: trunk@25374 -
 2013-08-26 17:41:54 +00:00
florian
d4968e054b + arm: tsettings.instructionset 
* the selected instruction set is now independent from the cpu type: e.g. armv7-a can perfectly execute thumb(2) code

git-svn-id: trunk@25370 -
 2013-08-25 21:56:12 +00:00
florian
7cef301e84 * disable optimization LdrbAnd2Ldrb for arm thumb as it is currently done 
git-svn-id: trunk@25356 -
 2013-08-23 18:41:26 +00:00
florian
f34bee1df7 * arm thumb does not support ror reg1,reg2,#imm 
git-svn-id: trunk@25355 -
 2013-08-23 18:41:24 +00:00
florian
950194678a * handle jump tables correctly when inserting constant pools on arm thumb 
git-svn-id: trunk@25354 -
 2013-08-23 18:41:21 +00:00
Károly Balogh
6591a24bd3 removed some code which must never be called, added an internalerror() instead 
git-svn-id: trunk@25352 -
 2013-08-23 15:58:37 +00:00
florian
e514e84c83 * first_moddivint should not change the return type if div/mul/add is used 
* use create_internal when creating internally add nodes

git-svn-id: trunk@25351 -
 2013-08-23 15:23:00 +00:00
florian
3ebe708574 * do not use r13/r15 for certain data processing operations 
* correct OP_AND with certain types of constants

git-svn-id: trunk@25350 -
 2013-08-23 15:22:58 +00:00
florian
2fe48077b2 * using r13 and r15 is on arm thumb2 also forbidden under certain conditions for the instructions A_SUB,A_AND,A_BIC,A_EOR 
git-svn-id: trunk@25349 -
 2013-08-23 15:22:55 +00:00
florian
d5ddf39f73 * do not do the RedundantMovProcess optimization when the involved registers are r13 or r15 and if the target is arm thumb(2) 
git-svn-id: trunk@25348 -
 2013-08-23 15:22:53 +00:00
florian
b4c7b40049 * do not split statements following A_IT* instructions on arm thumb2 when inserting constant pools 
git-svn-id: trunk@25347 -
 2013-08-23 15:22:51 +00:00
florian
8884f1c0bf * arm thumb2 supports only left shifted index registers up to 3 bits 
git-svn-id: trunk@25346 -
 2013-08-23 15:22:49 +00:00
florian
6df2917d93 * fix spilling of vfp instructions 
* spelling mistake fixed

git-svn-id: trunk@25345 -
 2013-08-23 15:22:46 +00:00
florian
c350c3a5e4 * arm thumb2 does not understand tst reg1,reg2,lsl reg3 
git-svn-id: trunk@25344 -
 2013-08-23 15:22:44 +00:00
florian
bb73a2891b * prevent generation of mul/mla statements with illegal registers 
git-svn-id: trunk@25343 -
 2013-08-23 15:22:41 +00:00
Jonas Maebe
4ec9ec2009 + PIC support for Darwin/ARM: 
o does not use GOT
   o enabled by default like for other Darwin platforms
  - removed Darwin/ARM call stub support: no longer needed with current
    Xcode versions (at least Xcode 4.2+), and we didn't support PIC
    in them yet

git-svn-id: trunk@25325 -
 2013-08-22 08:14:24 +00:00
Jonas Maebe
8ffb704b8c * don't split address labels from the instruction they belong with when 
rescheduling (needed for GOT-less PIC)

git-svn-id: trunk@25324 -
 2013-08-22 08:14:18 +00:00
Jonas Maebe
b31e5c2536 + PIC support for ARM jump tables (only for plain ARM right now, not 
yet for thumb/thumb2)

git-svn-id: trunk@25323 -
 2013-08-21 22:28:24 +00:00
florian
6606955b88 + basic support for pic on arm-linux 
git-svn-id: trunk@25297 -
 2013-08-19 21:35:37 +00:00
florian
2806947a8f + FindRegAllocBackward 
* search reg. allocations backward in RemoveSuperfluousMove because the changed instruction could be the first one in a list

git-svn-id: trunk@25289 -
 2013-08-18 18:56:56 +00:00
Jonas Maebe
57cdd8c106 * set symbol type/binding of data referred by ppc and arm/darwin stubs (part 
of r25264, fixes internalerror 2013081601 after r25266)

git-svn-id: trunk@25275 -
 2013-08-17 16:26:37 +00:00
Jonas Maebe
3b9b6a0cd7 * explicitly define the asmsymbols for Darwin call stubs as local 
git-svn-id: trunk@25264 -
 2013-08-16 10:07:46 +00:00
Károly Balogh
614afca755 ARM: try to inline 64bit multiplication for the most common cases instead of calling FPC_MUL_ helpers (results in 5-10x speedup) 
git-svn-id: trunk@25189 -
 2013-07-30 14:40:50 +00:00
florian
6f5bcaae2b * UMUL et al. have only register restrictions on arm below v6 
git-svn-id: trunk@25171 -
 2013-07-24 20:18:12 +00:00
Jeppe Johansen
d89b9a4311 Add support in ARM assembler reader for ldr reg, =literal syntax 
git-svn-id: trunk@25157 -
 2013-07-21 16:06:57 +00:00
Jeppe Johansen
fdcc68cfd7 Disabled preindex/postindexed peephole optimizations for Thumb and Thumb2 
git-svn-id: trunk@25156 -
 2013-07-21 14:21:16 +00:00
Jeppe Johansen
f3273fa87d Optimize Add/Sub+Ldr/Str by using preindexed references 
git-svn-id: trunk@24789 -
 2013-06-02 21:51:12 +00:00
Jeppe Johansen
2d823452b7 The scheduler pass of the ARM optimizer left markers in the instruction list, which could prevent further peephole optimizations 
git-svn-id: trunk@24781 -
 2013-06-02 16:37:41 +00:00
Jeppe Johansen
570b40faed Signed modulus by 2 on ARM with no division is optimized to a series of instructions instead of calling fpc_mod_longint. 
An ASR is removed from signed division by 2.

git-svn-id: trunk@24778 -
 2013-06-02 14:44:06 +00:00
Jonas Maebe
9938169d2c * don't use the paracgsize in get_paraloc_def(), because it generally 
contains the tcgsize of the entire parameter rather than only of
    what is left (-> calculate it from the remaining parameter length)

git-svn-id: trunk@24776 -
 2013-06-02 14:05:07 +00:00
Jonas Maebe
7566ddcc8f * add a tdef to each parameter location and set it for all target 
backends (not yet used, will be used in high level code generator)

git-svn-id: trunk@24761 -
 2013-06-02 10:24:02 +00:00
florian
4056194e7c * don't ignore by accident the next instruction after a newly inserted constant pool 
git-svn-id: trunk@24677 -
 2013-05-31 21:29:08 +00:00
florian
3a393f839e * do not reuse register locations on arm fpa/vfp 
git-svn-id: trunk@24676 -
 2013-05-31 21:29:05 +00:00
masta
8c32802fcf Added LdrbAnd2Ldrb Peephole optimizer for arm 
Changes the following code:
  ldrb dst1, [REF]
  and  dst2, dst1, #255
  # dealloc dst1
to
  ldrb dst2, [REF]

git-svn-id: trunk@24672 -
 2013-05-31 17:36:54 +00:00
Jonas Maebe
5051453806 + support for LOC_(C)MMREGISTER in hlcg 
o migrated location_force_mmregister_scalar from ncgutil to hlcgobj

git-svn-id: trunk@24661 -
 2013-05-31 12:05:14 +00:00
masta
073cab8d86 Optimize FoldShiftLdrStr in ARM Peephole optimizer 
The optimizer now juggles around the base and index register if that opens
up the possibility of folding the shift into the instruction.

This can only be done in the case of addressmode=AM_OFFSET, in case of
[AM_POSTINDEXED, AM_PREINDEXED] we can not move the base register, as this
would cause havoc and destruction.

git-svn-id: trunk@24645 -
 2013-05-30 16:13:58 +00:00
Jeppe Johansen
0bb8d24e24 Add some immediate forms of shift instructions to tcgthumb.a_op_const_reg 
git-svn-id: trunk@24637 -
 2013-05-30 12:07:32 +00:00
Jeppe Johansen
e5066a5f43 Update jumptabel generation for ARM Thumb 
git-svn-id: trunk@24636 -
 2013-05-30 12:06:30 +00:00
Jeppe Johansen
c4263ced51 Disable one peephole optimization for Thumb 
git-svn-id: trunk@24635 -
 2013-05-30 12:05:27 +00:00
florian
e6489ed7d2 * arm thumb: do not generate illegal ror instructions 
git-svn-id: trunk@24439 -
 2013-05-04 22:00:17 +00:00
florian
ccdd4437d6 * arm thumb: do not cause bxx getting too long ranges when inserting constant blocks 
git-svn-id: trunk@24437 -
 2013-05-04 20:36:08 +00:00
florian
7bea00e5fb * arm thumb: allow interface trampolines to non-virtual methods with large offsets 
git-svn-id: trunk@24434 -
 2013-05-04 19:54:03 +00:00
florian
ed2825fbb0 * arm thumb: handle constants in second_cmpsmallset correctly 
git-svn-id: trunk@24432 -
 2013-05-04 19:38:12 +00:00
florian
1de40c8de7 * arm thumb: fix spilling with offsets >1020 
git-svn-id: trunk@24419 -
 2013-05-04 10:51:01 +00:00
florian
6197330bad * arm thumb: take care of constant restrictions when creating interface wrappers for non-virtual methods 
git-svn-id: trunk@24415 -
 2013-05-03 21:12:16 +00:00
florian
f3b7f6197b * arm thumb: generate proper code for rol 
git-svn-id: trunk@24414 -
 2013-05-03 20:53:58 +00:00
florian
cec28ef512 * when inserting pc relative data blocks on arm thumb, avoid negative pc offsets, if needed, the data is copied 
a short test with the rtl shows that this happens exactly once in the rtl, so it is feasible to do so

git-svn-id: trunk@24413 -
 2013-05-03 20:45:26 +00:00
florian
0e9b8adb7a patch by Michael Ring: 
+ support of several armv6m MCUs for arm-embedded
* renamed lpc1343 unit to lpc13xx
+ more lpc13xx MCUs added

git-svn-id: trunk@24379 -
 2013-04-29 19:57:08 +00:00
florian
ec69ed5b3c * spelling fixed 
git-svn-id: trunk@24205 -
 2013-04-08 11:50:09 +00:00
florian
f80b6f4774 * arm thumb: take care of large offsets in interface wrappers 
git-svn-id: trunk@24203 -
 2013-04-07 21:56:37 +00:00
florian
dee35abf41 * arm thumb: let all registers used in a ldr/str operation interfere with the "hi" registers 
git-svn-id: trunk@24202 -
 2013-04-07 21:39:30 +00:00
florian
36a32e153d + arm thumb: tarmloadparentfpnode moves the stack pointer to a different register to avoid illegal instruction encodings 
git-svn-id: trunk@24201 -
 2013-04-07 21:29:12 +00:00
florian
e41b7b1b94 * arm thumb: strh/ldrh does not allow stack pointer based references with offset 
git-svn-id: trunk@24200 -
 2013-04-07 21:27:59 +00:00
florian
7ba197a221 * fix stack parameter handling for arm thumb 
* fix entry/exit code generation for arm thumb

git-svn-id: trunk@24197 -
 2013-04-07 21:01:15 +00:00
florian
f9ef8e90da + a_op_const_reg_reg for arm thumb taking care of availability of add sp,sp, ... 
* handle references with base and index on arm thumb correctly

git-svn-id: trunk@24196 -
 2013-04-07 21:01:11 +00:00
florian
9bbc24b5e3 * r13 might be used only under certain circumstance in memory reference on arm thumb 
git-svn-id: trunk@24195 -
 2013-04-07 21:01:08 +00:00
florian
79334242a2 * arm thumb uses always the stack pointer as frame pointer 
git-svn-id: trunk@24194 -
 2013-04-07 21:01:05 +00:00
florian
f25a905904 * fix register allocation initalization for arm thumb 
* avoid that the register allocator creates code which writes to frame/stack pointer

git-svn-id: trunk@24190 -
 2013-04-07 21:00:50 +00:00
florian
4e4cc4e289 * support neg instruction for spilling 
git-svn-id: trunk@24189 -
 2013-04-07 21:00:47 +00:00
florian
075abd6220 + support of stackframesize for arm thumb 
+ estimatedtempsize to get a good estimatation for architectures which require to know the stack size before

git-svn-id: trunk@24188 -
 2013-04-07 21:00:38 +00:00
Jonas Maebe
8b8a786823 * moved ARM/x86 ifdef'ed code from ncgcal to virtual methods 
git-svn-id: trunk@24179 -
 2013-04-07 13:42:06 +00:00
florian
93fcd9152e * arm thumb supports only tst reg1,reg2 
git-svn-id: trunk@23997 -
 2013-03-25 17:53:54 +00:00
florian
64bc09ae58 * fixes several issues with arm thumb stack frame 
git-svn-id: trunk@23988 -
 2013-03-24 21:40:23 +00:00
florian
b434b7bc7d * armv6-m has no blx <immediate> 
git-svn-id: trunk@23983 -
 2013-03-24 20:24:15 +00:00
florian
ac4a6accd3 + SVC instruction 
git-svn-id: trunk@23980 -
 2013-03-24 20:22:06 +00:00
florian
07762e5c25 + proper assembler command line parameters for arm thumb 
git-svn-id: trunk@23979 -
 2013-03-24 20:21:22 +00:00
florian
89b4939cec * correctly handle stackframes with size>508 for arm thumb 
git-svn-id: trunk@23977 -
 2013-03-24 18:51:23 +00:00
florian
c345ed8945 * generate branches for arm-thumb which are always sufficient big, the optimizer can fix this later on 
git-svn-id: trunk@23904 -
 2013-03-17 20:26:06 +00:00
florian
c2baf7b4c0 Merge r23058 
git-svn-id: trunk@23776 -
 2013-03-10 16:37:57 +00:00
florian
c0d4f189e9 * and takes three operands 
git-svn-id: trunk@23775 -
 2013-03-10 16:16:50 +00:00
florian
be81b89147 * fix bugs in previous commit 
git-svn-id: trunk@23774 -
 2013-03-10 14:33:10 +00:00
florian
086ae4b999 Merge r22905 and r22906 
git-svn-id: trunk@23773 -
 2013-03-10 10:45:34 +00:00
florian
21c154d60a Merged r22903 
git-svn-id: trunk@23757 -
 2013-03-09 20:56:07 +00:00
florian
08bf826334 Merges 22828,22829 
git-svn-id: trunk@23756 -
 2013-03-09 20:49:57 +00:00
florian
9198630ce3 * fix armv7m compiler 
git-svn-id: trunk@23686 -
 2013-03-03 21:59:34 +00:00
florian
1eeeb309c7 * intial armv6m support, it is not working yet, constant pool insertation and conditional branch fixup is not working yet 
git-svn-id: trunk@23682 -
 2013-03-03 12:20:10 +00:00
masta
96ed4e7932 Fixed access to freed memory in ShiftShiftShift2ShiftShift 1a on ARM 
ShiftShiftShift2ShiftShift tried to access a wrong and already freed
instruction the find out whatever a shift will result in a 0 result.

For some reason this only resulted in a bug on x86_64 linux host
crosscompiler builds.

git-svn-id: trunk@23624 -
 2013-02-17 00:01:00 +00:00
florian
bcd48ac1a1 + patch by Justin Smyth to support the lpc1343, resolves #23844 
git-svn-id: trunk@23620 -
 2013-02-14 20:38:53 +00:00
yury
e88bc322bc + Merge the targetandroid branch. Support for arm and i386 android targets. 
***************************************************************************

Revision: 23518
Author: yury
Date: 25 Jan 2013 0:14:31
Message:
* Build databases support for Android.
----
Modified : /branches/targetandroid/packages/dblib/fpmake.pp
Modified : /branches/targetandroid/packages/fcl-db/fpmake.pp

Revision: 23516
Author: yury
Date: 24 Jan 2013 23:08:12
Message:
* again made less complex for arm and sparc so it compiles there too without running out of registers.
----
Modified : /branches/targetandroid/tests/webtbs/tw2242.pp

Revision: 23515
Author: yury
Date: 24 Jan 2013 23:01:36
Message:
* Disabled the test for Android.
----
Modified : /branches/targetandroid/tests/webtbs/tw4038.pp

Revision: 23514
Author: yury
Date: 24 Jan 2013 22:32:39
Message:
* Disabled the test for Android.

----
Modified : /branches/targetandroid/tests/test/packages/webtbs/tw14265.pp

Revision: 23512
Author: yury
Date: 24 Jan 2013 12:30:07
Message:
* Allow passing of double quoted paths in TEST_OPT.
----
Modified : /branches/targetandroid/tests/Makefile
Modified : /branches/targetandroid/tests/Makefile.fpc

Revision: 23511
Author: yury
Date: 24 Jan 2013 12:29:01
Message:
* Fixed building of packages when cross-testing. Pass CROSSOPT to build packages in such case, otherwise options specified in TEST_OPT are used to build fpmake. The source compiler not always accepts target options. For example -Cfsoft option, often used for arm compiler, is not accepted by x86 compiler.
----
Modified : /branches/targetandroid/tests/tstunits/Makefile
Modified : /branches/targetandroid/tests/tstunits/Makefile.fpc

Revision: 23497
Author: yury
Date: 22 Jan 2013 19:10:54
Message:
* Reverted r23400 and r23401. Tomas has promised to commit more correct fix to trunk.
----
Modified : /branches/targetandroid/rtl/inc/fexpand.inc
Modified : /branches/targetandroid/tests/test/units/dos/tfexpand.pp

Revision: 23496
Author: yury
Date: 22 Jan 2013 19:05:51
Message:
* Disabled the test for Android.
----
Modified : /branches/targetandroid/tests/webtbs/tw0876.pp

Revision: 23495
Author: yury
Date: 22 Jan 2013 18:58:30
Message:
* Add %delfiles for proper clean-up.
----
Modified : /branches/targetandroid/tests/tbs/tb0582.pp
Modified : /branches/targetandroid/tests/test/tweaklib2.pp
Modified : /branches/targetandroid/tests/webtbs/tw12704b.pp
Modified : /branches/targetandroid/tests/webtbs/tw13628b.pp
Modified : /branches/targetandroid/tests/webtbs/tw14798.pp
Modified : /branches/targetandroid/tests/webtbs/tw16263b.pp
Modified : /branches/targetandroid/tests/webtbs/tw16949b.pp
Modified : /branches/targetandroid/tests/webtbs/tw2812.pp
Modified : /branches/targetandroid/tests/webtbs/tw3082.pp
Modified : /branches/targetandroid/tests/webtbs/tw3402.pp
Modified : /branches/targetandroid/tests/webtbs/tw6586b.pp
Modified : /branches/targetandroid/tests/webtbs/tw6822b.pp
Modified : /branches/targetandroid/tests/webtbs/tw7838b.pp
Modified : /branches/targetandroid/tests/webtbs/tw8730d.pp
Modified : /branches/targetandroid/tests/webtbs/tw9089c.pp

Revision: 23492
Author: yury
Date: 22 Jan 2013 16:43:42
Message:
* Turn off special handling of interrupt calling convention for i386-android.
----
Modified : /branches/targetandroid/compiler/i386/n386cal.pas
Modified : /branches/targetandroid/compiler/x86/cgx86.pas

Revision: 23491
Author: yury
Date: 22 Jan 2013 16:34:32
Message:
* Added %delfiles for proper clean-up.
----
Modified : /branches/targetandroid/tests/test/targ1b.pp
Modified : /branches/targetandroid/tests/test/tlib1b.pp
Modified : /branches/targetandroid/tests/test/tlib2b.pp
Modified : /branches/targetandroid/tests/test/tlibrary2.pp
Modified : /branches/targetandroid/tests/test/tlibrary3.pp
Modified : /branches/targetandroid/tests/test/units/sysutils/texec2.pp

Revision: 23490
Author: yury
Date: 22 Jan 2013 16:28:00
Message:
* These libs are for tests, that run only on windows. Mark libs for windows only as well.

----
Modified : /branches/targetandroid/tests/test/library/tlib3a.pp
Modified : /branches/targetandroid/tests/test/library/tlib3b.pp

Revision: 23489
Author: yury
Date: 22 Jan 2013 16:18:56
Message:
* Do not copy a library to a remote target if this library name is specified using %DELFILES directive.
----
Modified : /branches/targetandroid/tests/utils/dotest.pp

Revision: 23488
Author: yury
Date: 22 Jan 2013 15:47:52
Message:
* Implemented { %DELFILES file1 file2 ... } directive for tests. Primarily it is needed to delete shared libraries used by tests when TEST_DELTEMP=1. When testing on a real Android device, it is not good to run tests on flash memory partitions. Android devices have 1Mb RAM based tempfs partition for /tmp folder, which is ideal for running tests. Since 1Mb is very small size these days, it is needed to clean all test leftovers. Test shared libraries are the biggest leftovers and this new DELFILES directive will help to delete them.
* During remote execution, use && as a command separator after important commands such as CD to ensure that the command succeeded before running other commands. Group other commands using curly braces { }.
----
Modified : /branches/targetandroid/tests/readme.txt
Modified : /branches/targetandroid/tests/utils/dotest.pp
Modified : /branches/targetandroid/tests/utils/testu.pp

Revision: 23487
Author: yury
Date: 22 Jan 2013 13:16:22
Message:
* Define CExtended and clongdouble as double for Android.
----
Modified : /branches/targetandroid/compiler/psystem.pas
Modified : /branches/targetandroid/rtl/inc/ctypes.pp

Revision: 23486
Author: yury
Date: 22 Jan 2013 13:14:36
Message:
* Fixed compilation for case when extended <> cextended.
----
Modified : /branches/targetandroid/tests/test/cg/tcalext6.pp

Revision: 23485
Author: yury
Date: 22 Jan 2013 12:41:43
Message:
* More correct comparison of long double values for case when long double=double in C.
----
Modified : /branches/targetandroid/tests/test/cg/tcalext.pp

Revision: 23484
Author: yury
Date: 22 Jan 2013 11:53:41
Message:
* Do not pass -f switch for rm when testing via adb, since default android shell do not support -f switch.
----
Modified : /branches/targetandroid/tests/utils/dotest.pp

Revision: 23483
Author: yury
Date: 22 Jan 2013 11:47:31
Message:
* Added ICU version of Android 4.1.
* Increment by 2 when finding an unknown ICU version.
----
Modified : /branches/targetandroid/rtl/android/cwstring.pp

Revision: 23479
Author: yury
Date: 21 Jan 2013 14:29:40
Message:
* Add define for android.
----
Modified : /branches/targetandroid/tests/test/cg/tcalcst6.pp
Modified : /branches/targetandroid/tests/test/cg/tcalvar6.pp

Revision: 23478
Author: yury
Date: 21 Jan 2013 14:22:06
Message:
+ Added C object files for android-i386.
----
Added : /branches/targetandroid/tests/test/cg/obj/android/i386
Modified : /branches/targetandroid/tests/test/cg/obj/readme.txt

Revision: 23477
Author: yury
Date: 21 Jan 2013 14:08:25
Message:
* Add missing checks for android target.
----
Modified : /branches/targetandroid/compiler/aasmdata.pas
Modified : /branches/targetandroid/compiler/aggas.pas
Modified : /branches/targetandroid/compiler/expunix.pas
Modified : /branches/targetandroid/compiler/ncgld.pas
Modified : /branches/targetandroid/compiler/ogelf.pas
Modified : /branches/targetandroid/compiler/systems.pas
Modified : /branches/targetandroid/compiler/x86/agx86att.pas
Modified : /branches/targetandroid/compiler/x86/cgx86.pas
Modified : /branches/targetandroid/compiler/x86/rax86.pas

Revision: 23475
Author: yury
Date: 21 Jan 2013 13:51:09
Message:
* Set android-i368 stack alignment to 16.
----
Modified : /branches/targetandroid/compiler/systems/i_android.pas

Revision: 23474
Author: yury
Date: 21 Jan 2013 13:45:29
Message:
* Removed -z relro linker option, since it causes problems.
----
Modified : /branches/targetandroid/compiler/systems/t_android.pas

Revision: 23451
Author: yury
Date: 19 Jan 2013 1:32:26
Message:
* Pass some security switches to LD. They are passed by GCC.
* Removed unused function.
----
Modified : /branches/targetandroid/compiler/systems/t_android.pas

Revision: 23450
Author: yury
Date: 19 Jan 2013 1:27:45
Message:
* Fixed file description.
----
Modified : /branches/targetandroid/rtl/android/arm/dllprt0.as

Revision: 23449
Author: yury
Date: 19 Jan 2013 1:27:02
Message:
* Simplify arm startup code.
----
Modified : /branches/targetandroid/rtl/android/arm/prt0.as

Revision: 23448
Author: yury
Date: 19 Jan 2013 1:25:58
Message:
* Fixed file description.
----
Modified : /branches/targetandroid/rtl/android/i386/dllprt0.as
Modified : /branches/targetandroid/rtl/android/i386/prt0.as

Revision: 23447
Author: yury
Date: 19 Jan 2013 1:19:29
Message:
* Rewrite initialization code for i386-android. i386-android works.
----
Modified : /branches/targetandroid/rtl/android/i386/dllprt0.as
Modified : /branches/targetandroid/rtl/android/i386/prt0.as

Revision: 23441
Author: yury
Date: 18 Jan 2013 16:51:09
Message:
* Add android to supported targets for assemblers. It fixes assembling for i386-android.
----
Modified : /branches/targetandroid/compiler/arm/agarmgas.pas
Modified : /branches/targetandroid/compiler/i386/cpuelf.pas
Modified : /branches/targetandroid/compiler/x86/agx86att.pas

Revision: 23435
Author: yury
Date: 18 Jan 2013 0:46:23
Message:
* Enable safecall exception handling for arm-android.
----
Modified : /branches/targetandroid/compiler/systems/i_android.pas

Revision: 23434
Author: yury
Date: 18 Jan 2013 0:28:59
Message:
* Removed leftover from my experiments (calling directly pascal main).
----
Modified : /branches/targetandroid/rtl/android/arm/prt0.as

Revision: 23433
Author: yury
Date: 17 Jan 2013 23:43:09
Message:
* Uses SysUtils to make executable bigger. Otherwise string pointers for FindResource can be less than $10000. They are treated as IDs in such case and the test will fail.
----
Modified : /branches/targetandroid/tests/test/units/system/tres.pp

Revision: 23429
Author: yury
Date: 17 Jan 2013 18:49:23
Message:
* Thread safety.
----
Modified : /branches/targetandroid/rtl/android/cwstring.pp

Revision: 23427
Author: yury
Date: 17 Jan 2013 14:48:03
Message:
* Skip this test for android.
----
Modified : /branches/targetandroid/tests/test/textthr.pp

Revision: 23426
Author: yury
Date: 17 Jan 2013 14:21:51
Message:
* Fixed ifdefs linux to unix.
----
Modified : /branches/targetandroid/tests/test/tstring10.pp
Modified : /branches/targetandroid/tests/test/units/classes/tsetstream.pp
Modified : /branches/targetandroid/tests/test/units/dos/tdos.pp
Modified : /branches/targetandroid/tests/test/units/dos/tidos.pp

Revision: 23425
Author: yury
Date: 17 Jan 2013 14:20:56
Message:
* Enable more tests for android.
----
Modified : /branches/targetandroid/tests/test/packages/webtbs/tw14265.pp
Modified : /branches/targetandroid/tests/test/testfpuc.pp
Modified : /branches/targetandroid/tests/test/textthr.pp
Modified : /branches/targetandroid/tests/test/tlib2a.pp
Modified : /branches/targetandroid/tests/test/tlib2b.pp
Modified : /branches/targetandroid/tests/test/tpoll.pp
Modified : /branches/targetandroid/tests/test/tsafecall1.pp
Modified : /branches/targetandroid/tests/test/tsafecall2.pp
Modified : /branches/targetandroid/tests/test/tsafecall3.pp
Modified : /branches/targetandroid/tests/test/tsafecall4.pp
Modified : /branches/targetandroid/tests/test/units/system/tres.pp
Modified : /branches/targetandroid/tests/test/units/system/tres2.pp
Modified : /branches/targetandroid/tests/test/units/system/tres3.pp

Revision: 23424
Author: yury
Date: 17 Jan 2013 14:02:35
Message:
* Fixed AnsiStrLComp() and AnsiStrLIComp().
----
Modified : /branches/targetandroid/rtl/android/cwstring.pp

Revision: 23423
Author: yury
Date: 17 Jan 2013 13:49:55
Message:
* Fixed stupid copy-paste error.
----
Modified : /branches/targetandroid/rtl/android/cwstring.pp

Revision: 23409
Author: yury
Date: 16 Jan 2013 16:46:02
Message:
* Fixed conflict of native android and java android targets.
----
Modified : /branches/targetandroid/utils/fpcm/fpcmake.inc
Modified : /branches/targetandroid/utils/fpcm/fpcmake.ini

Revision: 23406
Author: yury
Date: 16 Jan 2013 15:33:50
Message:
* Set stackalign field.
----
Modified : /branches/targetandroid/compiler/systems/i_android.pas

Revision: 23404
Author: yury
Date: 16 Jan 2013 12:57:51
Message:
* Enable more tests for android.
----
Modified : /branches/targetandroid/tests/webtbs/tw0876.pp
Modified : /branches/targetandroid/tests/webtbs/tw12704a.pp
Modified : /branches/targetandroid/tests/webtbs/tw12704b.pp
Modified : /branches/targetandroid/tests/webtbs/tw16263a.pp
Modified : /branches/targetandroid/tests/webtbs/tw16263b.pp
Modified : /branches/targetandroid/tests/webtbs/tw16949a.pp
Modified : /branches/targetandroid/tests/webtbs/tw16949b.pp
Modified : /branches/targetandroid/tests/webtbs/tw6586a.pp
Modified : /branches/targetandroid/tests/webtbs/tw6586b.pp
Modified : /branches/targetandroid/tests/webtbs/tw6822c.pp
Modified : /branches/targetandroid/tests/webtbs/tw7838a.pp
Modified : /branches/targetandroid/tests/webtbs/tw7838b.pp
Modified : /branches/targetandroid/tests/webtbs/tw8730a.pp
Modified : /branches/targetandroid/tests/webtbs/tw8730b.pp
Modified : /branches/targetandroid/tests/webtbs/tw8730c.pp
Modified : /branches/targetandroid/tests/webtbs/tw8730d.pp
Modified : /branches/targetandroid/tests/webtbs/tw9089a.pp
Modified : /branches/targetandroid/tests/webtbs/tw9089b.pp
Modified : /branches/targetandroid/tests/webtbs/tw9089c.pp
Modified : /branches/targetandroid/tests/webtbs/tw9089d.pp
Modified : /branches/targetandroid/tests/webtbs/uw2364.pp

Revision: 23402
Author: yury
Date: 16 Jan 2013 12:50:52
Message:
* Use collation when comparing strings.
----
Modified : /branches/targetandroid/rtl/android/cwstring.pp

Revision: 23401
Author: yury
Date: 16 Jan 2013 12:41:32
Message:
* If there is no HOME directory, the current dir must be used.
----
Modified : /branches/targetandroid/tests/test/units/dos/tfexpand.pp

Revision: 23400
Author: yury
Date: 16 Jan 2013 12:40:25
Message:
* Fixed expanding ~ if there is no HOME env var set.
----
Modified : /branches/targetandroid/rtl/inc/fexpand.inc

Revision: 23391
Author: yury
Date: 15 Jan 2013 14:12:56
Message:
* Make sure that the thread has been started, before destroying the event.
----
Modified : /branches/targetandroid/tests/test/tbrtlevt.pp

Revision: 23390
Author: yury
Date: 15 Jan 2013 13:55:24
Message:
* Do not use DOS code pages for Android. Now all CP string tests pass on Android.
----
Modified : /branches/targetandroid/tests/test/tcpstr17.pp
Modified : /branches/targetandroid/tests/test/tcpstrconcat3.pp
Modified : /branches/targetandroid/tests/test/tcpstrconcatmulti.pp
Modified : /branches/targetandroid/tests/test/tcpstrconcatmulti2.pp

Revision: 23389
Author: yury
Date: 15 Jan 2013 13:53:50
Message:
* Use more common code pages 1251 and 1252 instead of old DOS code pages (not available on Android). There is Euro symbol character that has different code in 1251 and 1252 code pages. Use it for tests.
----
Modified : /branches/targetandroid/tests/test/tcpstr1.pp
Modified : /branches/targetandroid/tests/test/tcpstransistrcompare.pp
Modified : /branches/targetandroid/tests/test/tcpstransistrcompareequal.pp

Revision: 23386
Author: yury
Date: 15 Jan 2013 10:22:30
Message:
* Skip 2 tests for android, since they require local execution.
----
Modified : /branches/targetandroid/tests/test/tcpstr19.pp
Modified : /branches/targetandroid/tests/test/tcpstr9.pp

Revision: 23385
Author: yury
Date: 15 Jan 2013 10:20:43
Message:
* Fixed running library tests on android.
----
Modified : /branches/targetandroid/tests/utils/dotest.pp

Revision: 23382
Author: yury
Date: 14 Jan 2013 16:20:44
Message:
* Implemented Unicode string manager for Android. It uses ICU library libicuuc.so. Note: ICU on Android has limited number of code pages. So don't expect support for DOS code pages or other exotic code pages.
----
Modified : /branches/targetandroid/rtl/android/cwstring.pp

Revision: 23301
Author: yury
Date: 2 Jan 2013 20:47:09
Message:
* I've found that libc on Android does not implement widechar case functions such as towupper(). Such functions are just wrappers over regular char functions. Therefore the whole cwstring unit is useless for Android. For now I've added stub cwstring unit for Android and reverted all Android specific changes in unix/cwstring.pp. Later, Unicode manager for Androud should be implemented using libicuuc, which is default Android lib.
----
Added : /branches/targetandroid/rtl/android/cwstring.pp
Modified : /branches/targetandroid/rtl/unix/cwstring.pp

Revision: 23299
Author: yury
Date: 2 Jan 2013 19:38:08
Message:
* Android does not have libiconv, so don't use it in cwstring unit. For now support only UTF-8 code page in ansistrings. Later it is possible to use libicuuc for code page conversions on Android.
----
Modified : /branches/targetandroid/rtl/unix/cwstring.pp

Revision: 23298
Author: yury
Date: 2 Jan 2013 17:41:36
Message:
* Added uuchar unit to build for android.
----
Modified : /branches/targetandroid/rtl/android/Makefile
Modified : /branches/targetandroid/rtl/android/Makefile.fpc

Revision: 23289
Author: yury
Date: 2 Jan 2013 2:53:36
Message:
* Always specify dynamic linker name for executables.
----
Modified : /branches/targetandroid/compiler/systems/t_android.pas

Revision: 23288
Author: yury
Date: 2 Jan 2013 2:04:41
Message:
* Updated Makefile
----
Modified : /branches/targetandroid/rtl/android/Makefile

Revision: 23287
Author: yury
Date: 2 Jan 2013 2:03:42
Message:
* cprt0.as is not needed, since we link to libc always.
----
Modified : /branches/targetandroid/rtl/android/Makefile.fpc

Revision: 23286
Author: yury
Date: 2 Jan 2013 2:01:43
Message:
* cprt0.as is not needed, since we link to libc always.
----
Modified : /branches/targetandroid/rtl/android/Makefile.fpc
Deleted : /branches/targetandroid/rtl/android/arm/cprt0.as
Deleted : /branches/targetandroid/rtl/android/i386/cprt0.as

Revision: 23285
Author: yury
Date: 2 Jan 2013 1:59:48
Message:
* libctype is not needed, since only bionic is supported anyway.
----
Modified : /branches/targetandroid/compiler/systems/t_android.pas

Revision: 23284
Author: yury
Date: 2 Jan 2013 1:49:12
Message:
* Rework of Android startup code. It is needed to always link to libc on android to implement finalization and environment variables in shared libraries.
* Cleanup of Android linker.
* Use only INSERT command in the linker script to inject custom .fpc sections. Whole linker script duplication is nor needed anymore.
* Use BFD linker, since GOLD linker does not support INSERT command. Other incompatibilities may also exist.
* Enable tf_smartlink_sections for i386-android.
* i386-android is broken after this commit. Will be fixed later.
----
Modified : /branches/targetandroid/compiler/systems/i_android.pas
Modified : /branches/targetandroid/compiler/systems/t_android.pas
Modified : /branches/targetandroid/rtl/android/arm/dllprt0.as
Modified : /branches/targetandroid/rtl/android/arm/prt0.as

Revision: 23283
Author: yury
Date: 2 Jan 2013 1:48:07
Message:
* Enable weak externals for android.
----
Modified : /branches/targetandroid/compiler/systems.pas

Revision: 23236
Author: yury
Date: 28 Dec 2012 12:42:27
Message:
* Oops, wrong commit r23235. Reverted. Now correct: Fixed lineinfo for Android.
----
Modified : /branches/targetandroid/rtl/inc/exeinfo.pp
Modified : /branches/targetandroid/tests/test/units/sysutils/texec2.pp

Revision: 23235
Author: yury
Date: 28 Dec 2012 11:38:04
Message:
* Fixed lineinfo for Android.
----
Modified : /branches/targetandroid/tests/test/units/sysutils/texec2.pp

Revision: 23232
Author: yury
Date: 27 Dec 2012 22:52:26
Message:
* Fixed the test for android.
----
Modified : /branches/targetandroid/tests/test/units/dos/tdos2.pp

Revision: 23231
Author: yury
Date: 27 Dec 2012 22:51:32
Message:
+ Added C object files for arm-android.
----
Added : /branches/targetandroid/tests/test/cg/obj/android
Added : /branches/targetandroid/tests/test/cg/obj/android/arm
Added : /branches/targetandroid/tests/test/cg/obj/android/arm/cpptcl1.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm/cpptcl2.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm/ctest.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm/tcext3.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm/tcext4.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm/tcext5.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm/tcext6.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi/cpptcl1.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi/cpptcl2.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi/ctest.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi/tcext3.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi/tcext4.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi/tcext5.o
Added : /branches/targetandroid/tests/test/cg/obj/android/arm-eabi/tcext6.o

Revision: 23226
Author: yury
Date: 27 Dec 2012 10:17:06
Message:
* Support for running tests on a remote Android device using ADB.
----
Modified : /branches/targetandroid/tests/Makefile
Modified : /branches/targetandroid/tests/Makefile.fpc
Modified : /branches/targetandroid/tests/readme.txt
Modified : /branches/targetandroid/tests/tstunits/Makefile
Modified : /branches/targetandroid/tests/utils/dotest.pp

Revision: 22048
Author: tom_at_work
Date: 9 Aug 2012 17:13:51
Message:
re-apply the changes of r22045 to correct files after recent revert
----
Modified : /branches/targetandroid/rtl/android/arm/cprt0.as
Added : /branches/targetandroid/rtl/android/i386
Added : /branches/targetandroid/rtl/android/i386/cprt0.as
Added : /branches/targetandroid/rtl/android/i386/dllprt0.as
Added : /branches/targetandroid/rtl/android/i386/prt0.as

Revision: 22047
Author: tom_at_work
Date: 9 Aug 2012 16:57:34
Message:
- revert r22045: applied changes to wrong files, i.e. linux system files, instead of android ones
----
Modified : /branches/targetandroid/rtl/android/arm/cprt0.as
Modified : /branches/targetandroid/rtl/linux/i386/cprt0.as
Added : /branches/targetandroid/rtl/linux/i386/cprt21.as
Added : /branches/targetandroid/rtl/linux/i386/gprt21.as

Revision: 22045
Author: tom_at_work
Date: 9 Aug 2012 11:05:38
Message:
Made cprt0 startup files to compile. Static executables using them likely do not work though.
Removed obsolete startup files (?prt21*).

----
Modified : /branches/targetandroid/rtl/android/arm/cprt0.as
Modified : /branches/targetandroid/rtl/linux/i386/cprt0.as
Deleted : /branches/targetandroid/rtl/linux/i386/cprt21.as
Deleted : /branches/targetandroid/rtl/linux/i386/gprt21.as

Revision: 22044
Author: tom_at_work
Date: 9 Aug 2012 11:00:16
Message:
Updated systems/t_android to only recognize the "bionic" libc as valid libc.
Fix uninitialized defdynlinker variable when compiling i386-android causing garbage in the linker script.

----
Modified : /branches/targetandroid/compiler/systems/t_android.pas

Revision: 21296
Author: tom_at_work
Date: 15 May 2012 0:14:12
Message:
* basic android/x86 support
----
Modified : /branches/targetandroid/Makefile
Modified : /branches/targetandroid/compiler/Makefile
Modified : /branches/targetandroid/compiler/i386/cputarg.pas
Modified : /branches/targetandroid/compiler/systems/i_android.pas
Modified : /branches/targetandroid/compiler/systems/t_android.pas
Modified : /branches/targetandroid/compiler/systems.inc
Modified : /branches/targetandroid/compiler/systems.pas
Modified : /branches/targetandroid/compiler/utils/Makefile
Modified : /branches/targetandroid/compiler/utils/ppudump.pp
Modified : /branches/targetandroid/ide/Makefile
Modified : /branches/targetandroid/ide/compiler/Makefile
Modified : /branches/targetandroid/installer/Makefile
Modified : /branches/targetandroid/packages/Makefile
Modified : /branches/targetandroid/packages/fpmkunit/Makefile
Modified : /branches/targetandroid/rtl/Makefile
Modified : /branches/targetandroid/rtl/aix/Makefile
Modified : /branches/targetandroid/rtl/amiga/Makefile
Modified : /branches/targetandroid/rtl/android/Makefile
Modified : /branches/targetandroid/rtl/android/Makefile.fpc
Modified : /branches/targetandroid/rtl/beos/Makefile
Modified : /branches/targetandroid/rtl/darwin/Makefile
Modified : /branches/targetandroid/rtl/embedded/Makefile
Modified : /branches/targetandroid/rtl/emx/Makefile
Modified : /branches/targetandroid/rtl/freebsd/Makefile
Modified : /branches/targetandroid/rtl/gba/Makefile
Modified : /branches/targetandroid/rtl/go32v2/Makefile
Modified : /branches/targetandroid/rtl/haiku/Makefile
Modified : /branches/targetandroid/rtl/linux/Makefile
Modified : /branches/targetandroid/rtl/macos/Makefile
Modified : /branches/targetandroid/rtl/morphos/Makefile
Modified : /branches/targetandroid/rtl/nativent/Makefile
Modified : /branches/targetandroid/rtl/nds/Makefile
Modified : /branches/targetandroid/rtl/netbsd/Makefile
Modified : /branches/targetandroid/rtl/netware/Makefile
Modified : /branches/targetandroid/rtl/netwlibc/Makefile
Modified : /branches/targetandroid/rtl/openbsd/Makefile
Modified : /branches/targetandroid/rtl/os2/Makefile
Modified : /branches/targetandroid/rtl/palmos/Makefile
Modified : /branches/targetandroid/rtl/solaris/Makefile
Modified : /branches/targetandroid/rtl/symbian/Makefile
Modified : /branches/targetandroid/rtl/unix/x86.pp
Modified : /branches/targetandroid/rtl/wii/Makefile
Modified : /branches/targetandroid/rtl/win32/Makefile
Modified : /branches/targetandroid/rtl/win64/Makefile
Modified : /branches/targetandroid/rtl/wince/Makefile
Modified : /branches/targetandroid/utils/Makefile
Modified : /branches/targetandroid/utils/dxegen/Makefile
Modified : /branches/targetandroid/utils/fpcm/Makefile
Modified : /branches/targetandroid/utils/fpcm/fpcmmain.pp
Modified : /branches/targetandroid/utils/fpcmkcfg/Makefile
Modified : /branches/targetandroid/utils/fpcres/Makefile
Modified : /branches/targetandroid/utils/fpcreslipo/Makefile
Modified : /branches/targetandroid/utils/fpdoc/Makefile
Modified : /branches/targetandroid/utils/fpmc/Makefile
Modified : /branches/targetandroid/utils/fppkg/Makefile
Modified : /branches/targetandroid/utils/fprcp/Makefile
Modified : /branches/targetandroid/utils/h2pas/Makefile
Modified : /branches/targetandroid/utils/importtl/Makefile
Modified : /branches/targetandroid/utils/instantfpc/Makefile
Modified : /branches/targetandroid/utils/rmwait/Makefile
Modified : /branches/targetandroid/utils/tply/Makefile

Revision: 21066
Author: tom_at_work
Date: 26 Apr 2012 22:05:06
Message:
fix pthreads use with Android: it does not provide some functions. This patch is partially based on the bug report 0021525. Further, fix use of sem_timedwait in cthreads.pp since Android supports it.
----
Modified : /branches/targetandroid/rtl/linux/pthread.inc
Modified : /branches/targetandroid/rtl/unix/cthreads.pp

Revision: 21065
Author: tom_at_work
Date: 26 Apr 2012 16:15:52
Message:
bugfixes:
- do not compile ipc unit for android, not supported
- fix geterrnolocation external name
- implement dummy getdomainname; does not exist in android
- remove wrong 'if defined(android)' clauses
----
Modified : /branches/targetandroid/rtl/android/Makefile
Modified : /branches/targetandroid/rtl/android/Makefile.fpc
Modified : /branches/targetandroid/rtl/fpmake.pp
Modified : /branches/targetandroid/rtl/unix/cwstring.pp
Modified : /branches/targetandroid/rtl/unix/initc.pp
Modified : /branches/targetandroid/rtl/unix/ipc.pp
Modified : /branches/targetandroid/rtl/unix/unix.pp

Revision: 21063
Author: tom_at_work
Date: 26 Apr 2012 12:53:37
Message:
- missing makefile
----
Added : /branches/targetandroid/rtl/android/Makefile

Revision: 21062
Author: tom_at_work
Date: 26 Apr 2012 12:41:13
Message:
- commit missing new files
----
Added : /branches/targetandroid/compiler/systems/i_android.pas
Added : /branches/targetandroid/compiler/systems/t_android.pas
Added : /branches/targetandroid/rtl/android
Added : /branches/targetandroid/rtl/android/Makefile.fpc
Added : /branches/targetandroid/rtl/android/arm
Added : /branches/targetandroid/rtl/android/arm/cprt0.as
Added : /branches/targetandroid/rtl/android/arm/dllprt0.as
Added : /branches/targetandroid/rtl/android/arm/prt0.as

Revision: 21061
Author: tom_at_work
Date: 26 Apr 2012 12:36:42
Message:
- initial support for the android/arm target in the compiler; resulting .so's can be used for Android/ARM app development.
- basic rtl support using system calls
- fp(c)make/fppkg/makefile support

todo:
- revisit systems/t_android.pas: mostly duplicate with t_linux.pas, containing
lots of unnecessary code
- revisit rtl changes
- android ndk header translation import
- better app build/packaging support
- android/x86 support

----
Modified : /branches/targetandroid/Makefile
Modified : /branches/targetandroid/compiler/Makefile
Modified : /branches/targetandroid/compiler/aggas.pas
Modified : /branches/targetandroid/compiler/arm/cputarg.pas
Modified : /branches/targetandroid/compiler/compiler.pas
Modified : /branches/targetandroid/compiler/systems.inc
Modified : /branches/targetandroid/compiler/systems.pas
Modified : /branches/targetandroid/compiler/utils/Makefile
Modified : /branches/targetandroid/compiler/utils/ppudump.pp
Modified : /branches/targetandroid/ide/Makefile
Modified : /branches/targetandroid/ide/compiler/Makefile
Modified : /branches/targetandroid/installer/Makefile
Modified : /branches/targetandroid/packages/Makefile
Modified : /branches/targetandroid/packages/fpmkunit/Makefile
Modified : /branches/targetandroid/packages/fpmkunit/Makefile.fpc
Modified : /branches/targetandroid/packages/fpmkunit/src/fpmkunit.pp
Modified : /branches/targetandroid/packages/fppkg/src/fpmkunitsrc.inc
Modified : /branches/targetandroid/packages/gnome1/fpmake.pp
Modified : /branches/targetandroid/packages/gtk1/fpmake.pp
Modified : /branches/targetandroid/packages/gtk2/fpmake.pp
Modified : /branches/targetandroid/packages/imlib/fpmake.pp
Modified : /branches/targetandroid/packages/opengl/fpmake.pp
Modified : /branches/targetandroid/packages/sdl/fpmake.pp
Modified : /branches/targetandroid/rtl/Makefile
Modified : /branches/targetandroid/rtl/Makefile.fpc
Modified : /branches/targetandroid/rtl/aix/Makefile
Modified : /branches/targetandroid/rtl/amiga/Makefile
Modified : /branches/targetandroid/rtl/beos/Makefile
Modified : /branches/targetandroid/rtl/darwin/Makefile
Modified : /branches/targetandroid/rtl/embedded/Makefile
Modified : /branches/targetandroid/rtl/emx/Makefile
Modified : /branches/targetandroid/rtl/freebsd/Makefile
Modified : /branches/targetandroid/rtl/gba/Makefile
Modified : /branches/targetandroid/rtl/go32v2/Makefile
Modified : /branches/targetandroid/rtl/haiku/Makefile
Modified : /branches/targetandroid/rtl/linux/Makefile
Modified : /branches/targetandroid/rtl/macos/Makefile
Modified : /branches/targetandroid/rtl/morphos/Makefile
Modified : /branches/targetandroid/rtl/nativent/Makefile
Modified : /branches/targetandroid/rtl/nds/Makefile
Modified : /branches/targetandroid/rtl/netbsd/Makefile
Modified : /branches/targetandroid/rtl/netware/Makefile
Modified : /branches/targetandroid/rtl/netwlibc/Makefile
Modified : /branches/targetandroid/rtl/openbsd/Makefile
Modified : /branches/targetandroid/rtl/os2/Makefile
Modified : /branches/targetandroid/rtl/palmos/Makefile
Modified : /branches/targetandroid/rtl/solaris/Makefile
Modified : /branches/targetandroid/rtl/symbian/Makefile
Modified : /branches/targetandroid/rtl/unix/cwstring.pp
Modified : /branches/targetandroid/rtl/unix/initc.pp
Modified : /branches/targetandroid/rtl/unix/ipc.pp
Modified : /branches/targetandroid/rtl/unix/unix.pp
Modified : /branches/targetandroid/rtl/wii/Makefile
Modified : /branches/targetandroid/rtl/win32/Makefile
Modified : /branches/targetandroid/rtl/win64/Makefile
Modified : /branches/targetandroid/rtl/wince/Makefile
Modified : /branches/targetandroid/utils/Makefile
Modified : /branches/targetandroid/utils/dxegen/Makefile
Modified : /branches/targetandroid/utils/fpcm/Makefile
Modified : /branches/targetandroid/utils/fpcm/fpcmake.inc
Modified : /branches/targetandroid/utils/fpcm/fpcmake.ini
Modified : /branches/targetandroid/utils/fpcm/fpcmmain.pp
Modified : /branches/targetandroid/utils/fpcmkcfg/Makefile
Modified : /branches/targetandroid/utils/fpcmkcfg/fppkg.inc
Modified : /branches/targetandroid/utils/fpcres/Makefile
Modified : /branches/targetandroid/utils/fpcreslipo/Makefile
Modified : /branches/targetandroid/utils/fpdoc/Makefile
Modified : /branches/targetandroid/utils/fpmc/Makefile
Modified : /branches/targetandroid/utils/fppkg/Makefile
Modified : /branches/targetandroid/utils/fppkg/fppkg.pp
Modified : /branches/targetandroid/utils/fprcp/Makefile
Modified : /branches/targetandroid/utils/h2pas/Makefile
Modified : /branches/targetandroid/utils/importtl/Makefile
Modified : /branches/targetandroid/utils/instantfpc/Makefile
Modified : /branches/targetandroid/utils/rmwait/Makefile
Modified : /branches/targetandroid/utils/tply/Makefile

git-svn-id: trunk@23604 -
 2013-02-13 12:00:15 +00:00
florian
ef1c848198 * fix constant calculation for the AndAnd2And optimization if the first and is removed, noticed by Nico Erfurth 
git-svn-id: trunk@23541 -
 2013-01-29 20:39:22 +00:00
svenbarth
7bad1763b8 Decrease amount of code duplication regarding handling of safecall and record constructors. 
paramgr.pas, tparamanager:
    + add new method "handle_common_ret_in_param"
    * extract common code (safecall + record constructor handling) from "ret_in_param" to "handle_common_ret_in_param" and call the latter in "ret_in_param"
[aarch64,arm,avr,i386,x86_64]/cpupara.pas, tCPUparamanager.ret_in_param:
    * call "handle_common_ret_in_param" instead of implementing the same check again and again
ncgcal.pas, tcgcallnode.handle_return_value:
    * move the check for (record) constructors to "tparamanager.handle_common_ret_in_param"

git-svn-id: trunk@23520 -
 2013-01-25 20:39:28 +00:00
yury
d8902af3d6 * Do not replace ADD by SUB and vice-versa when overflow checking is enabled. Fixes tw15304 for ARM. 
git-svn-id: trunk@23517 -
 2013-01-24 21:49:21 +00:00
yury
8ae7c5784c * Sync with trunk r23500. 
git-svn-id: branches/targetandroid@23501 -
 2013-01-23 07:53:13 +00:00
florian
9d76168b57 * refactored Bl2B condition code to make it more readable 
git-svn-id: trunk@23464 -
 2013-01-20 15:38:38 +00:00
florian
7184306a4c + option -Wx to generate thumb interworking safe code on arm 
git-svn-id: trunk@23463 -
 2013-01-20 15:26:59 +00:00
florian
3fff969ced * take care of instruction in between when doing ShiftShiftShift2ShiftShift optimizations 
git-svn-id: trunk@23462 -
 2013-01-20 14:58:03 +00:00
florian
f1b8fad6dc * make AndAnd2And working with other instructions in between 
git-svn-id: trunk@23461 -
 2013-01-20 14:57:59 +00:00
florian
fcef2dc3df * refactored some code and introduced usage of new method RegEndOfLife 
git-svn-id: trunk@23460 -
 2013-01-20 14:57:55 +00:00
florian
82f3ec7922 * if cs_opt_level3 is not set, limit lookahead of GetNextInstructionUsingReg to one instruction: 
only -O3 means do the really slow optimizations

git-svn-id: trunk@23459 -
 2013-01-20 14:57:51 +00:00
florian
a78af5b8fe + AndLslXsr2And and AndLsl2Lsl optimization 
git-svn-id: trunk@23458 -
 2013-01-20 14:57:46 +00:00
florian
ff522d7e18 * improve ShiftShiftShift2ShiftShift to look further ahead 
* check register usage so the destination register can be different

git-svn-id: trunk@23457 -
 2013-01-20 14:57:43 +00:00
florian
12d0c05ede * remove bic instructions after lsr if possible 
git-svn-id: trunk@23456 -
 2013-01-20 14:57:38 +00:00
yury
c2fed960c9 * Add android to supported targets for assemblers. It fixes assembling for i386-android. 
git-svn-id: branches/targetandroid@23441 -
 2013-01-18 14:51:09 +00:00
florian
abfa6c1b43 * redo LsrAnd2Lsr optimization 
git-svn-id: trunk@23413 -
 2013-01-16 20:24:07 +00:00
masta
fe520c215b New ARM Peephole optimizer FoldShiftLdrStr 
This one folds
      mov r1, r2, lsl #2
      ldr/ldrb r0, [r0, r1]
into
      ldr/ldrb r0, [r0, r2, lsl #2]

There is still some room for improvement, maybe it would be better to do this before
the register allocator runs, as we'll currently waste a register (r1 in the above example)
in many cases. That would also allow to to fold more operations, because currently if r2
gets reused between the mov and ldr we'll not be able to do the optimization.

git-svn-id: trunk@23408 -
 2013-01-16 14:37:28 +00:00
yury
d26f0552a0 * Sync with trunk r23404. 
* Regenerated makefiles.

git-svn-id: branches/targetandroid@23405 -
 2013-01-16 13:21:51 +00:00
paul
b2a613c17f compiler: implement record constructors + tests 
git-svn-id: trunk@23395 -
 2013-01-16 02:07:42 +00:00
paul
51825b6f2e compiler: change ret_in_param to accept tabstractprocdef instead of tproccalloption to allow check more options (required for record constructor implementation) 
git-svn-id: trunk@23394 -
 2013-01-16 01:14:23 +00:00
sergei
32ffddaad8 + ELF linker back-ends for ARM and MIPS. 
ARM status: roughly corresponds to i386 one, passes the test suite. Handles libraries, can link static libc code including basic PIC and TLS IE/LE stuff. Completely misses Thumb support. Also does not handle ABI-specific stuff, for this reason internally linked .so cannot be used for linking executables with ld. Little-endian only. Tested only on "versatilepb" QEMU virtual machine.

MIPS status: can link the compiler and at least some dynamic executables including fpmake. Some PIC support is present but almost untested. Specific header flags and sections are also not handled yet. Written to handle both endian, but tested for big-endian only ("malta" QEMU VM), including cross-linking from x86_64.

git-svn-id: trunk@23376 -
 2013-01-13 18:05:19 +00:00
Jonas Maebe
69c29a415f * pass the procdef to getintparaloc instead of only the proccalloption, so 
that the type of the parameters can be determined automatically
   o added compilerproc declarations for all helpers called in the compiler
     via their assembler name, so we can look up the corresponding procdef

git-svn-id: trunk@23325 -
 2013-01-06 15:05:40 +00:00
masta
6fabe49828 Readded cutils to compiler/arm/rgcpu.pas for DEBUG_SPILLING 
Commit r23306 broke compiling with DEBUG_SPILLING set. Unit cutils will
now be included when DEBUG_SPILLING is set.

git-svn-id: trunk@23308 -
 2013-01-04 12:21:54 +00:00
florian
47d43750e4 * remove unused units from uses statements 
git-svn-id: trunk@23306 -
 2013-01-03 23:07:09 +00:00
florian
903f18ea38 * get rid of calls which redirect the program flow only, Bl2B optimization 
git-svn-id: trunk@23279 -
 2013-01-01 19:31:52 +00:00
florian
ff98d2567c * don't crash on thumb instructions with only two operands when optimizing ADD, SUB, AND statements 
git-svn-id: trunk@23272 -
 2013-01-01 12:29:48 +00:00
masta
e982f4789d Removed unused register allocation in tarminlinenode.second_abs_long 
git-svn-id: trunk@23047 -
 2012-11-22 19:20:39 +00:00
Jeppe Johansen
3ee29eb219 Fixed ARMv7-EM code generation and RTL compilation 
Added LM4F120H5 controller type and startup code

git-svn-id: branches/laksen/arm-embedded@22903 -
 2012-11-01 17:25:01 +00:00
masta
1261d6617d Properly handle MVN in RedundantMovProcess for ARM 
RedundantMovProcess will now also handle MVN, folding

mov r0, r1
mvn r0, r0

into

mvn r0, r1

git-svn-id: trunk@22878 -
 2012-10-29 22:53:37 +00:00
masta
3a017f76d0 Look ahead more than one instruction in FoldShiftProcess for ARM 
Up until now we only checked the next instruction, with the new load
scheduler this is insufficient as shift-instructions and next usage
might farther apart.

The new version uses GetNextInstructionUsingReg, this also comes with a
price as we very carefully have to check if one of the used registers is
changed and that the usage of RRX will not break when we fold and flags
get changed in between.

git-svn-id: trunk@22876 -
 2012-10-29 17:57:11 +00:00
florian
3143f0e1be * fix by Jeppe Johansen for bitscan which was broken by the last fix for normal arm code 
git-svn-id: trunk@22866 -
 2012-10-28 17:57:22 +00:00
tom_at_work
312e8b8ecc Add implementations for read/write barrier code for ARM 
git-svn-id: trunk@22864 -
 2012-10-27 22:53:44 +00:00
florian
1520bcc4f0 * fix bsf for armv7+ 
git-svn-id: trunk@22860 -
 2012-10-27 20:17:58 +00:00
florian
8221681871 + add spilling info for the RBIT instruction 
git-svn-id: trunk@22859 -
 2012-10-27 20:17:12 +00:00
florian
8c73b0b17b * disable broken MvnAnd2Bic optimization 
git-svn-id: trunk@22847 -
 2012-10-25 17:51:25 +00:00
Jeppe Johansen
b34915c4ad Disabled MLA/MLS optimization for now 
git-svn-id: branches/laksen/arm-embedded@22829 -
 2012-10-23 12:49:41 +00:00
Jeppe Johansen
818b43c060 Updated localalign values, and changed the behaviour of alignment of load/stores to not break aligned half-word copies 
git-svn-id: branches/laksen/arm-embedded@22828 -
 2012-10-23 12:45:40 +00:00
florian
eeef57a2a1 * merging more of Jeppe Johansen's arm-embedded branch 
git-svn-id: trunk@22824 -
 2012-10-22 21:12:29 +00:00
masta
e91b15b2a4 Disabled MulAdd2MLA and MulSub2MLS Peephole optimizers for thumb2 
According to Jeppe Johansen these are currently broken and emit the
operands in the wrong order.

git-svn-id: trunk@22822 -
 2012-10-22 15:30:24 +00:00
masta
e327b4581c Use TRegNameTable instead of array[tregisterindex] of string[10] 
TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.

r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.

git-svn-id: trunk@22817 -
 2012-10-22 10:23:21 +00:00
florian
7150832ec9 + Cortex-M3 special registers, resolves #23185 
git-svn-id: trunk@22815 -
 2012-10-21 20:06:07 +00:00
Jeppe Johansen
628d46f2d3 Fixed Bsf* functions on platforms that support RBIT 
Fixed stackframe epilogue code for Thumb2 to allow proper processing of interrupts

git-svn-id: branches/laksen/arm-embedded@22813 -
 2012-10-21 19:13:59 +00:00
florian
970405c0f3 o merging r22801 of Jeppe Johansen 
git-svn-id: trunk@22812 -
 2012-10-21 19:05:59 +00:00
Jeppe Johansen
4e84431dde Fix some optimizations which assume that there are 3 operands 
Add simple Mul+Sub/Mul+Add into MLS/MLA optimizations
Fix some other small issues in the optimizer
Implement Interlocked* functions with proper use of LDREX/STREX

git-svn-id: branches/laksen/arm-embedded@22801 -
 2012-10-21 16:20:52 +00:00
Jonas Maebe
6497d3c994 - removed no longer used/supported af_allowdirect flag (direct assembler 
reader support)

git-svn-id: trunk@22794 -
 2012-10-21 13:42:58 +00:00
florian
04543b179f o merge of the branch laksen/arm-embedded of Jeppe Johansen: 
fixes a couple of arm-embedded stuff, 
  adds some controllers, start of fpv4_s16 support, for a complete list of
  changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line

Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line

Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line

Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line

Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines

Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line

Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line

Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line

Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines

Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines

Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines

Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines

Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines

Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines

Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)

git-svn-id: trunk@22792 -
 2012-10-21 08:39:52 +00:00
Jeppe Johansen
5751bbecee Properly do NR_DEFAULTFLAGS detection/allocation/deallocation 
git-svn-id: branches/laksen/arm-embedded@22787 -
 2012-10-20 20:00:36 +00:00
Jeppe Johansen
3558a40bf6 Fixed flags detections code for wide->short optimization code for Thumb-2 
git-svn-id: branches/laksen/arm-embedded@22782 -
 2012-10-20 05:44:55 +00:00
Jeppe Johansen
666332385d Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 
git-svn-id: branches/laksen/arm-embedded@22778 -
 2012-10-19 18:23:14 +00:00
pierre
a8591af2a9 Handle po_nostackframe for arm cpu 
git-svn-id: trunk@22720 -
 2012-10-18 11:41:57 +00:00
florian
a95641e43c * don't pass march always to gas because the rtl uses always pld to be able 
to chose the right code path at runtime

git-svn-id: trunk@22709 -
 2012-10-17 19:58:11 +00:00
Jeppe Johansen
84ea70fddc Fixed some minor formating issues 
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)

git-svn-id: branches/laksen/arm-embedded@22646 -
 2012-10-14 19:10:20 +00:00
masta
aef7361f9f Fix RemoveSuperfluousMov in ARM Peephole optimizers. 
The last patch (r22622) got the condition wrong.

git-svn-id: trunk@22624 -
 2012-10-12 22:33:45 +00:00
masta
938c8f1ee1 Fix regLoadedWithNewValue for A_STR on ARM 
The function regLoadedWithNewValue returned true if the oper[0].reg
matched in an STR instruction, which is wrong as it will only be read.

git-svn-id: trunk@22623 -
 2012-10-12 22:33:40 +00:00
masta
29bac200dd Fix interaction between peephole optimizers on ARM 
Up until now DataMov2Data could be run on an strb generated by
AndStrb2Strb.

Code like this:

and  reg0, reg1, #255
strb reg0, [r13]
mov  reg2,reg1

would get transformed into:

strb reg2, [r13]

which is clearly wrong. The problem was that DataMov2Data expected that
it's first parameter is an instruction which loads new data into
oper[0]. With the introduction of AndStrb2Strb this wasn't true anymore.

This fix now checks if the first register is actually written to, this
is done by using regLoadedWithNewValue.

git-svn-id: trunk@22622 -
 2012-10-12 21:30:40 +00:00
Jeppe Johansen
14879a9e82 Added all STM32F1 configurations 
git-svn-id: branches/laksen/arm-embedded@22599 -
 2012-10-09 06:58:58 +00:00
Jeppe Johansen
a8f9b0dac4 Added initial support for the Cortex-M4F FPv4_S16 FPU 
git-svn-id: branches/laksen/arm-embedded@22597 -
 2012-10-08 20:10:45 +00:00
Jeppe Johansen
0087661fb5 Added FPv4_d16 FPU instructions, and a few extra registers 
git-svn-id: branches/laksen/arm-embedded@22596 -
 2012-10-08 20:04:14 +00:00
Jeppe Johansen
3e963a49e2 Added support for IT block merging 
Added a peephole pattern check for UXTB->UXTH chains

git-svn-id: branches/laksen/arm-embedded@22592 -
 2012-10-08 14:07:40 +00:00
Jeppe Johansen
9ec9b44784 Add CBNZ/CBZ instructions 
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions

git-svn-id: branches/laksen/arm-embedded@22590 -
 2012-10-08 12:30:00 +00:00
Jeppe Johansen
b788ba660d Fix optimizations of Thumb-2 code 
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.

git-svn-id: branches/laksen/arm-embedded@22582 -
 2012-10-08 04:49:39 +00:00
Jeppe Johansen
80bb3febea Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines 
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts

git-svn-id: branches/laksen/arm-embedded@22581 -
 2012-10-08 03:15:40 +00:00
Jeppe Johansen
8e00978108 Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader 
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements

git-svn-id: branches/laksen/arm-embedded@22580 -
 2012-10-08 03:10:44 +00:00
Jeppe Johansen
8b17a358e4 Remove all traces of the interrupt vector table generation mechanism 
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)

git-svn-id: branches/laksen/arm-embedded@22579 -
 2012-10-08 00:10:52 +00:00
tom_at_work
f4ba47a1c8 Fixed --march parameter passed to GNU as for ARM processors 
git-svn-id: trunk@22541 -
 2012-10-04 21:47:28 +00:00
florian
54d3d736f5 * patch by Jeppe Johansen to add support for handling different flags for xPSR regs, 
and add usermode parsing of LDM/STM ops
  This patch basically extends the ARM assembly reader a bit to properly parse CPSR and 
  SPSR flags for the MSR opcode, and allows the reader to understand 
  the ^ modifer for register lists for STMxx and LDMxx.

  Previously the following combinations weren't possible in straight assembler:
     MRS R0, CPSR
     MRS R0, SPSR
     MSR CPSR_CX, R0
     LDMIA SP, {R0-R15}^
     etc.. 

git-svn-id: trunk@22502 -
 2012-09-29 08:23:40 +00:00
Jonas Maebe
1a97e61619 * factored out fixref from handle_load_store, and handle indirect symbol 
loads for darwin in fixref (used to be done in ncgld, but was removed
    there)

git-svn-id: trunk@22445 -
 2012-09-23 21:25:32 +00:00
masta
c3a91c5022 Remove the postfix check in MovStrMov peephole optimizer for ARM 
We don't need to check for the postfix, PF_NONE/PF_H/PF_B are all ok for us and
can be intermixed. This allows the peephole optimizer to work for
strb and strh instructions.

git-svn-id: trunk@22367 -
 2012-09-10 14:57:43 +00:00
masta
0f40429389 Improve handling of set operations with constant values on ARM 
tarmaddnode.second_cmpsmallset always forced a value into a register
even when it could be represented as a constant, resulting in wasted
registers.

mov r1, #5
cmp r0, r1

If possible we'll now create:
cmp r0, #5

git-svn-id: trunk@22366 -
 2012-09-10 12:37:50 +00:00
florian
7840b4657a * the improved arm optimizer might move instructions around so the old hacky test if a label with its data has been already embedded into the code by checking if the offset is 0 does not work anymore so a new field for tai_label has been introduced for this purpose 
git-svn-id: trunk@22345 -
 2012-09-06 15:12:17 +00:00
florian
03bf93488b * workaround for broken in operator 
git-svn-id: trunk@22329 -
 2012-09-05 15:00:04 +00:00
florian
3b980cae63 * floating point compares use flags as well so allocate flags 
git-svn-id: trunk@22328 -
 2012-09-05 15:00:00 +00:00
florian
de34eab23d + optimize and ...,255/strb ... sequence if possible 
git-svn-id: trunk@22323 -
 2012-09-05 11:24:03 +00:00
florian
93d0033282 * improve AndAnd2And optimization by checking if the first destination register is allocated after the second and 
git-svn-id: trunk@22322 -
 2012-09-05 11:23:05 +00:00
florian
8a6c65b008 * fix r22319: hp1 must have the same condition as p 
git-svn-id: trunk@22321 -
 2012-09-05 09:05:26 +00:00
florian
2f1989c1a6 * hp1 can have any condition in this case so don't access hp1.condition because it 
is not guranteed that hp1 is actually a tai_instruction before calling MatchInstruction

git-svn-id: trunk@22319 -
 2012-09-04 18:58:28 +00:00
florian
5facc6ad5e * BsrX(0) should return 255 instead of $ffffffff 
git-svn-id: trunk@22316 -
 2012-09-04 15:16:59 +00:00
florian
d67af82228 * patch by Jeppe Johansen: Thumb2-only targets don't support the BLX <label>, and have to use BL <label>, resolves #22770 
git-svn-id: trunk@22314 -
 2012-09-04 14:57:26 +00:00
florian
d63ebe6464 * bsr implementation for armv5+ using clz 
git-svn-id: trunk@22310 -
 2012-09-04 12:56:38 +00:00
florian
91156f8652 + cpuflag CPUARM_HAS_CLZ for arm 
git-svn-id: trunk@22309 -
 2012-09-04 12:56:27 +00:00
florian
59012afe26 * better heuristics to decide when a mul by a constant shall be replaced by shift/add/sub sequences 
git-svn-id: trunk@22300 -
 2012-09-03 13:39:52 +00:00
florian
2f8027c63f + more sophisticated code to optimize multiplications on arm 
+ the multiplication optimization needs a popcnt function
+ simple test

git-svn-id: trunk@22299 -
 2012-09-03 13:39:45 +00:00
masta
d8af83d252 Introduce a version of MatchInstruction for multiple instructions 
It is the same as the normal MatchInstruction function but supports to
be called with a set of TAsmOps instead of a single op.

git-svn-id: trunk@22231 -
 2012-08-24 15:54:36 +00:00
florian
6b73bc45c5 * check constant for being a valid offset 
git-svn-id: trunk@22230 -
 2012-08-24 09:16:47 +00:00
florian
58a85e79ce * set index register correctly * index register might not be changed 
git-svn-id: trunk@22229 -
 2012-08-24 09:16:38 +00:00
florian
245d8286d5 + LookForPostindexedPattern 
git-svn-id: trunk@22228 -
 2012-08-24 09:16:26 +00:00
masta
012da673a8 Use MatchInstruction in OpCmp2OpS 
MatchInstruction keeps the code a bit more readable and compact.

git-svn-id: trunk@22226 -
 2012-08-23 23:08:26 +00:00
florian
a016bc5ced * white space change 
git-svn-id: trunk@22224 -
 2012-08-23 21:04:31 +00:00
florian
f2ccd6e400 * when doing the AddSubLdr2Ldr optimization check also if the source register of the add is modified before the load 
git-svn-id: trunk@22223 -
 2012-08-23 21:04:21 +00:00
florian
4e2de05667 * don't apply the AddSubLdr2Ldr optimization if the base register in the reference is used/modified during the ldr/str 
git-svn-id: trunk@22222 -
 2012-08-23 21:04:11 +00:00
florian
d89b742109 * apply Add/SubLdr2Ldr only if no condition flags are involved 
git-svn-id: trunk@22221 -
 2012-08-23 21:04:02 +00:00
florian
73d540e7b5 * unsigned byte ldr/str allow also an offset of max. +/-4095 
git-svn-id: trunk@22220 -
 2012-08-23 21:03:52 +00:00
florian
9d20a73986 * optimize also str/ldrb/h/d 
git-svn-id: trunk@22219 -
 2012-08-23 21:03:44 +00:00
florian
1b3e03d72d + DEBUG_AOPTCPU to turn off peephole optimizer messages 
git-svn-id: trunk@22218 -
 2012-08-23 21:03:34 +00:00
florian
8a20ccc5f9 + Add/SubLdr2Ldr optimization 
git-svn-id: trunk@22217 -
 2012-08-23 21:03:24 +00:00
masta
b9fa9da629 Small fixes to OpCmp2OpS 
1.) For UMULL and UMLAL support we would have to make sure the following
code checks RdHi and RdLo, which is currently not supported.
The former code would transform the following

  umull r0, r1, r2, r3
  cmp   r0, #0
  bne   .LSomething

into

  umulls r0,r1,r2,r3
  bne    .LSomething

which is wrong. UMULL has a 64bit result in r1+r0 and checks the full 64bit for 0
before setting the Z flag.

2.) Support MLA.

3.) Support MI/PL/NE/EQ for all instructions. As all of them are setting
the N and Z flags in the same way only based on the result of the
operation not on its input values.

N:=Result[31];
Z:=Result = 0;

Wurst

git-svn-id: trunk@22213 -
 2012-08-23 14:22:29 +00:00
florian
3ad32b6e4e * opcode spelling fixed 
git-svn-id: trunk@22204 -
 2012-08-23 08:55:07 +00:00
florian
935985d0c0 * checked and updated valid opcode for OpCmp2OpS optimization 
git-svn-id: trunk@22203 -
 2012-08-23 08:55:03 +00:00
florian
70009e8ed1 * move flag allocation item 
git-svn-id: trunk@22202 -
 2012-08-23 08:54:58 +00:00
florian
45383fd32d + a lot missing flag allocs/deallocs added 
git-svn-id: trunk@22201 -
 2012-08-23 08:54:52 +00:00
florian
2d2c66467c + optimize op ... / cmp .... when possible 
git-svn-id: trunk@22200 -
 2012-08-23 08:54:47 +00:00
florian
a92ca7c456 * adjust the reg. allocations of the target register in RemoveSuperfluousMove 
git-svn-id: trunk@22194 -
 2012-08-22 19:52:37 +00:00
florian
3d7b603d11 * get rid or move the allocation of the replaced register if possible 
git-svn-id: trunk@22193 -
 2012-08-22 19:52:30 +00:00
florian
77e579f59f * RemoveSuperfluousMove uses FindRegDeAlloc to find out if the register used in the move can be removed 
* RemoveSuperfluousMove fixes partially the register allocation changes caused by the mov

git-svn-id: trunk@22192 -
 2012-08-22 19:52:23 +00:00
florian
5fd457e586 * when determining of a register is used after an instruction, new allocs should not be taken into account 
git-svn-id: trunk@22189 -
 2012-08-22 19:52:03 +00:00
florian
c0425c48fd * make use of GetNextInstructionUsingReg 
git-svn-id: trunk@22186 -
 2012-08-22 19:51:40 +00:00
florian
f3f5be2af1 * RemoveSuperfluousMove should not mess with moves targetting lr or pc 
git-svn-id: trunk@22185 -
 2012-08-22 19:51:31 +00:00
florian
93eb20d407 + GetNextInstructionUsingReg 
git-svn-id: trunk@22184 -
 2012-08-22 19:51:19 +00:00
florian
55e6da6d28 * make cpubase for arm use inlining 
git-svn-id: trunk@22183 -
 2012-08-22 19:51:08 +00:00
florian
d8161c185c + track usage of flags by using a new register RS_/NR_DEFAULTFLAGS 
git-svn-id: trunk@22179 -
 2012-08-22 19:37:51 +00:00
florian
2a14394cf5 * cleaned up scheduler code, created own scheduler class to avoid unneeded passes through the assembler 
git-svn-id: trunk@22133 -
 2012-08-19 19:15:34 +00:00
florian
a3bf956c33 * improved main loop of TCpuPreRegallocScheduler.PeepHoleOptPass1Cpu 
* reordered conditions in scheduler main loop so they abort potentially quicker

git-svn-id: trunk@22132 -
 2012-08-19 19:13:49 +00:00
florian
765fb18679 + add a description to the cpuflags where I know the exact meaning/definition 
git-svn-id: trunk@22119 -
 2012-08-17 20:45:46 +00:00
florian
54e2b40ab4 * revert the parameter type change of the last commit, it was an overleft from a failed fix attempt 
git-svn-id: trunk@22116 -
 2012-08-17 19:36:37 +00:00
florian
ba6ba52e7f * instruction scheduling is pretty slow so make it a level 3 optimization for now 
git-svn-id: trunk@22115 -
 2012-08-17 19:36:29 +00:00
florian
45eafd3e65 * fix MovMov optimization if the second mov is a mov rX,rX 
git-svn-id: trunk@22114 -
 2012-08-17 19:36:22 +00:00
florian
4b4e08c28b * fixes copy&paste errors when moving end of live pointers 
git-svn-id: trunk@22113 -
 2012-08-17 19:36:16 +00:00
florian
53a0d3e3a3 * fixed typo when checking live start of references 
git-svn-id: trunk@22112 -
 2012-08-17 19:36:10 +00:00
florian
5ceeb8aaa9 * enable scheduler when compiling at least with -O2 
git-svn-id: trunk@22111 -
 2012-08-17 19:36:04 +00:00
florian
a693fe9fb7 + implemented TCpuPreRegallocScheduler.SwapRegLive and make use of it to be able to reschedule instructions before register allocation 
git-svn-id: trunk@22110 -
 2012-08-17 19:35:59 +00:00
florian
7e5b8584cf * set MaxOps to 4 for the optimizer because fpc generates now mla instructions 
git-svn-id: trunk@22106 -
 2012-08-17 12:38:59 +00:00
florian
354cac2bb6 + completed arm architectures 
* ldrd/strd and pld collected under the edsp define

git-svn-id: trunk@22104 -
 2012-08-17 10:37:27 +00:00
florian
7588896775 * make use of cpuflags in the arm compiler 
* armv5te architecture

git-svn-id: trunk@22103 -
 2012-08-17 10:37:17 +00:00
florian
e4f89fe524 + introduce cpuflags for arm 
git-svn-id: trunk@22090 -
 2012-08-15 15:49:05 +00:00
florian
ecb037ad79 + tarminnode.pass_1 to set expectloc correctly 
git-svn-id: trunk@22074 -
 2012-08-13 15:03:35 +00:00
florian
d2aa35e9de * throw an internal error if code generation depends on expectloc but expectloc and real loc do not match 
git-svn-id: trunk@22073 -
 2012-08-13 15:02:55 +00:00
florian
33f287d320 + tarminnode.in_smallset making use of tst 
git-svn-id: trunk@22064 -
 2012-08-11 22:10:45 +00:00
florian
19debd87cc * start with a qword aligned frame pointer to enable more ldrd/strd optimizations 
git-svn-id: trunk@22061 -
 2012-08-11 15:12:19 +00:00
florian
371ef7bada * cover more cases in AlignedToQWord 
git-svn-id: trunk@22060 -
 2012-08-11 15:11:43 +00:00
florian
db7e029574 * strd/ldrd optimization might be only done on dword operations 
git-svn-id: trunk@22059 -
 2012-08-11 15:11:10 +00:00
florian
8c45a909be + support ldr/ldr -> ldrd and str/str -> strd optimization where appliable 
git-svn-id: trunk@22058 -
 2012-08-11 11:45:54 +00:00
florian
4d86d25c6c * -O4 switch for optimizations which are correct but which might have unexpected effects 
like field reordering (possible problems cracker classes) or using ebp as normal register (broken
      stack traces from dump_stack)
    + niln is also valid in a cse domain
    * parameters passed by reference shall have a complexity >1
    * load nodes from outer scopes shall have a complexity >1
    * better cse debugging
    + more node types added to cse
    * consider parameters passed by reference in cse
    * take care of cse in parameters in simple cases

git-svn-id: trunk@22050 -
 2012-08-09 18:58:54 +00:00
tom_at_work
810adb2f65 Merge with trunk r22040. Regenerated makefiles. 
git-svn-id: branches/targetandroid@22046 -
 2012-08-09 08:12:34 +00:00
florian
b330bba0bc + introduce -Oofastmath 
* limit the application of the tree transformation introduced in r21986 to safe cases and -Oofastmath

git-svn-id: trunk@22040 -
 2012-08-08 19:35:45 +00:00
masta
aa21845cd9 Small optimization for OP_AND on ARM 
Especially with 64bit operators the CG sometimes generates:
and r0, r1, #0
Which just clears r0 and is equivalent with
mov r0, #0

git-svn-id: trunk@22032 -
 2012-08-08 06:44:20 +00:00
florian
7513291ad8 * generate different code for OS_S8 -> OS_16 conversion which might fold better, idea by Nico Erfurth 
git-svn-id: trunk@22027 -
 2012-08-07 19:36:46 +00:00
masta
6529307d9e Don't emit useless AND/BICs in ARM CG 
In certain cases the CG would emit something like
bic r1, r0, #0
As BIC is clearing the specified bits this is equivalent to
mov r1, r0
This patch changes the CG to emit the mov instead which the register
allocator will hopefully remove most of the time.

git-svn-id: trunk@22024 -
 2012-08-07 06:46:45 +00:00
masta
9e039936bf Support more operators in FoldShiftProcess on ARM 
Now we can also fold shifts into teq, tst, cmp, cmn instructions.

git-svn-id: trunk@22023 -
 2012-08-07 06:46:32 +00:00
florian
f619a1aaf6 * fld/fst can have a base register+offset 
git-svn-id: trunk@22016 -
 2012-08-05 18:34:13 +00:00
florian
e81ba0f82e + make use of the armv6+ sign/zero extension instructions if appropriate 
git-svn-id: trunk@22013 -
 2012-08-05 14:04:11 +00:00
florian
eb1efdff8a + introduce cstylearrayofconst because pocall_mwcall was forgotten at several places 
git-svn-id: trunk@22012 -
 2012-08-05 08:48:23 +00:00